xref: /linux/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi (revision 06d07429858317ded2db7986113a9e0129cd599b)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Gateworks Corporation
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>

/ {
	aliases {
		ethernet1 = &eth1;
		usb0 = &usbotg1;
		usb1 = &usbotg2;
	};

	led-controller {
		compatible = "gpio-leds";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_leds>;

		led-0 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};

		led-1 {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_RED>;
			gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
			default-state = "off";
		};
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pps {
		compatible = "pps-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pps>;
		gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_usb_otg1_vbus: regulator-usb-otg1 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1_en>;
		compatible = "regulator-fixed";
		regulator-name = "usb_otg1_vbus";
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_usb_otg2_vbus: regulator-usb-otg2 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb2_en>;
		compatible = "regulator-fixed";
		regulator-name = "usb_otg2_vbus";
		gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};
};

/* off-board header */
&ecspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spi2>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
		   <&gpio1 10 GPIO_ACTIVE_LOW>;
	status = "okay";

	tpm@1 {
		compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
		reg = <0x1>;
		spi-max-frequency = <36000000>;
	};
};

&gpio1 {
	gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
		"", "", "pci_usb_sel", "dio0",
		"", "dio1", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&gpio4 {
	gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
		"mipi_gpio1", "", "", "pci_wdis#",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	accelerometer@19 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_accel>;
		compatible = "st,lis2de12";
		reg = <0x19>;
		st,drdy-int-pin = <1>;
		interrupt-parent = <&gpio4>;
		interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
	};
};

/* off-board header */
&i2c3 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&pcie_phy {
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
	fsl,clkreq-unsupported;
	clocks = <&pcie0_refclk>;
	clock-names = "ref";
	status = "okay";
};

&pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>,
		 <&clk IMX8MM_CLK_PCIE1_AUX>;
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				 <&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";

	pcie@0,0 {
		reg = <0x0000 0 0 0 0>;
		device_type = "pci";
		#address-cells = <3>;
		#size-cells = <2>;
		ranges;

		pcie@0,0 {
			reg = <0x0000 0 0 0 0>;
			device_type = "pci";
			#address-cells = <3>;
			#size-cells = <2>;
			ranges;

			pcie@3,0 {
				reg = <0x1800 0 0 0 0>;
				device_type = "pci";
				#address-cells = <3>;
				#size-cells = <2>;
				ranges;

				eth1: ethernet@0,0 {
					reg = <0x0000 0 0 0 0>;
					#address-cells = <3>;
					#size-cells = <2>;
					ranges;

					local-mac-address = [00 00 00 00 00 00];
				};
			};
		};
	};
};

/* off-board header */
&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "okay";
};

/* GPS */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* off-board header */
&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

/* RS232 */
&uart4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart4>;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	over-current-active-low;
	vbus-supply = <&reg_usb_otg1_vbus>;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	vbus-supply = <&reg_usb_otg2_vbus>;
	status = "okay";
};

/* microSD */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	vmmc-supply = <&reg_3p3v>;
	status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	pinctrl_hog: hoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x40000041 /* PLUG_TEST */
			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6	0x40000041 /* PCI_USBSEL */
			MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7	0x40000041 /* PCIE_WDIS# */
			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x40000041 /* DIO0 */
			MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9	0x40000041 /* DIO1 */
			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0	0x40000104 /* RS485_TERM */
			MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0	0x40000104 /* RS485 */
			MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2	0x40000104 /* RS485_HALF */
		>;
	};

	pinctrl_accel: accelgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5	0x159
		>;
	};

	pinctrl_gpio_leds: gpioledgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5	0x19
			MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x19
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6	0x41
		>;
	};

	pinctrl_pps: ppsgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x41
		>;
	};

	pinctrl_reg_usb1_en: regusb1grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x41
			MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC	0x41
		>;
	};

	pinctrl_reg_usb2_en: regusb2grp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8	0x41
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
			MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
		>;
	};

	pinctrl_spi2: spi2grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0xd6
			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0xd6
			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0xd6
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0xd6
			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10	0xd6
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
		>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
			MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B	0x1d0
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};
};