xref: /linux/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dtso (revision 55d0969c451159cff86949b38c39171cab962069)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Gateworks Corporation
4 *
5 * GW72xx RS422 (RS485 full duplex):
6 *  - GPIO1_0 rs485_term selects on-chip termination
7 *  - GPIO4_0 rs485_en needs to be driven high (active)
8 *  - GPIO4_2 rs485_hd needs to be driven low (in-active)
9 *  - UART4_TX is DE for RS485 transmitter
10 *  - RS485_EN needs to be pulled high
11 *  - RS485_HALF needs to be low
12 */
13
14#include <dt-bindings/gpio/gpio.h>
15
16#include "imx8mm-pinfunc.h"
17
18/dts-v1/;
19/plugin/;
20
21&gpio4 {
22	rs485-en-hog {
23		gpio-hog;
24		gpios = <0 GPIO_ACTIVE_HIGH>;
25		output-high;
26		line-name = "rs485_en";
27	};
28
29	rs485-hd-hog {
30		gpio-hog;
31		gpios = <2 GPIO_ACTIVE_HIGH>;
32		output-low;
33		line-name = "rs485_hd";
34	};
35};
36
37&uart2 {
38	pinctrl-names = "default";
39	pinctrl-0 = <&pinctrl_uart2>;
40	rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
41	linux,rs485-enabled-at-boot-time;
42	status = "okay";
43};
44
45&uart4 {
46	status = "disabled";
47};
48
49&iomuxc {
50	pinctrl_uart2: uart2grp {
51		fsl,pins = <
52			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
53			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
54			MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29	0x140
55		>;
56	};
57};
58