1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10/ { 11 aliases { 12 usb0 = &usbotg1; 13 usb1 = &usbotg2; 14 }; 15 16 led-controller { 17 compatible = "gpio-leds"; 18 pinctrl-names = "default"; 19 pinctrl-0 = <&pinctrl_gpio_leds>; 20 21 led-0 { 22 function = LED_FUNCTION_STATUS; 23 color = <LED_COLOR_ID_GREEN>; 24 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 25 default-state = "on"; 26 linux,default-trigger = "heartbeat"; 27 }; 28 29 led-1 { 30 function = LED_FUNCTION_STATUS; 31 color = <LED_COLOR_ID_RED>; 32 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 33 default-state = "off"; 34 }; 35 }; 36 37 pcie0_refclk: pcie0-refclk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <100000000>; 41 }; 42 43 pps { 44 compatible = "pps-gpio"; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_pps>; 47 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; 48 status = "okay"; 49 }; 50}; 51 52&ecspi2 { 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_spi2>; 55 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, 56 <&gpio1 10 GPIO_ACTIVE_LOW>; 57 status = "okay"; 58 59 tpm@1 { 60 compatible = "tcg,tpm_tis-spi"; 61 reg = <0x1>; 62 spi-max-frequency = <36000000>; 63 }; 64}; 65 66&gpio1 { 67 gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0", 68 "", "dio1", "", "", "", "", "", "", 69 "", "", "", "", "", "", "", "", 70 "", "", "", "", "", "", "", ""; 71}; 72 73&gpio4 { 74 gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#", 75 "", "", "", "", "", "", "", "", 76 "", "", "", "", "", "", "", "", 77 "", "", "", "", "", "", "", ""; 78}; 79 80&i2c2 { 81 clock-frequency = <400000>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_i2c2>; 84 status = "okay"; 85 86 accelerometer@19 { 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_accel>; 89 compatible = "st,lis2de12"; 90 reg = <0x19>; 91 st,drdy-int-pin = <1>; 92 interrupt-parent = <&gpio4>; 93 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 94 }; 95}; 96 97/* off-board header */ 98&i2c3 { 99 clock-frequency = <400000>; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_i2c3>; 102 status = "okay"; 103}; 104 105&pcie_phy { 106 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 107 fsl,clkreq-unsupported; 108 clocks = <&pcie0_refclk>; 109 clock-names = "ref"; 110 status = "okay"; 111}; 112 113&pcie0 { 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_pcie0>; 116 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; 117 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 118 <&clk IMX8MM_CLK_PCIE1_AUX>; 119 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 120 <&clk IMX8MM_CLK_PCIE1_CTRL>; 121 assigned-clock-rates = <10000000>, <250000000>; 122 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 123 <&clk IMX8MM_SYS_PLL2_250M>; 124 status = "okay"; 125}; 126 127/* GPS */ 128&uart1 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_uart1>; 131 status = "okay"; 132}; 133 134/* off-board header */ 135&uart3 { 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_uart3>; 138 status = "okay"; 139}; 140 141&usbotg1 { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_usbotg1>; 144 dr_mode = "otg"; 145 over-current-active-low; 146 status = "okay"; 147}; 148 149&usbotg2 { 150 dr_mode = "host"; 151 disable-over-current; 152 status = "okay"; 153}; 154 155&iomuxc { 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_hog>; 158 159 pinctrl_hog: hoggrp { 160 fsl,pins = < 161 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ 162 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ 163 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ 164 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ 165 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ 166 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */ 167 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */ 168 >; 169 }; 170 171 pinctrl_accel: accelgrp { 172 fsl,pins = < 173 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 174 >; 175 }; 176 177 pinctrl_gpio_leds: gpioledgrp { 178 fsl,pins = < 179 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 180 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 181 >; 182 }; 183 184 pinctrl_i2c3: i2c3grp { 185 fsl,pins = < 186 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 187 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 188 >; 189 }; 190 191 pinctrl_pcie0: pcie0grp { 192 fsl,pins = < 193 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 194 >; 195 }; 196 197 pinctrl_pps: ppsgrp { 198 fsl,pins = < 199 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 200 >; 201 }; 202 203 pinctrl_spi2: spi2grp { 204 fsl,pins = < 205 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 206 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 207 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 208 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 209 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 210 >; 211 }; 212 213 pinctrl_uart1: uart1grp { 214 fsl,pins = < 215 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 216 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 217 >; 218 }; 219 220 pinctrl_uart3: uart3grp { 221 fsl,pins = < 222 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 223 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 224 >; 225 }; 226 227 pinctrl_usbotg1: usbotg1grp { 228 fsl,pins = < 229 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x141 230 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 231 >; 232 }; 233}; 234