1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> 5 */ 6 7#include "imx8mm.dtsi" 8 9/ { 10 model = "Variscite VAR-SOM-MX8MM module"; 11 12 chosen { 13 stdout-path = &uart4; 14 }; 15 16 memory@40000000 { 17 device_type = "memory"; 18 reg = <0x0 0x40000000 0 0x80000000>; 19 }; 20 21 reg_eth_phy: regulator-eth-phy { 22 compatible = "regulator-fixed"; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_reg_eth_phy>; 25 regulator-name = "eth_phy_pwr"; 26 regulator-min-microvolt = <3300000>; 27 regulator-max-microvolt = <3300000>; 28 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; 29 enable-active-high; 30 }; 31}; 32 33&A53_0 { 34 cpu-supply = <&buck2_reg>; 35}; 36 37&A53_1 { 38 cpu-supply = <&buck2_reg>; 39}; 40 41&A53_2 { 42 cpu-supply = <&buck2_reg>; 43}; 44 45&A53_3 { 46 cpu-supply = <&buck2_reg>; 47}; 48 49&ddrc { 50 operating-points-v2 = <&ddrc_opp_table>; 51 52 ddrc_opp_table: opp-table { 53 compatible = "operating-points-v2"; 54 55 opp-25000000 { 56 opp-hz = /bits/ 64 <25000000>; 57 }; 58 59 opp-100000000 { 60 opp-hz = /bits/ 64 <100000000>; 61 }; 62 63 opp-750000000 { 64 opp-hz = /bits/ 64 <750000000>; 65 }; 66 }; 67}; 68 69&ecspi1 { 70 pinctrl-names = "default"; 71 pinctrl-0 = <&pinctrl_ecspi1>; 72 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, 73 <&gpio1 0 GPIO_ACTIVE_LOW>; 74 /delete-property/ dmas; 75 /delete-property/ dma-names; 76 status = "okay"; 77 78 /* Resistive touch controller */ 79 touchscreen@0 { 80 reg = <0>; 81 compatible = "ti,ads7846"; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_restouch>; 84 interrupt-parent = <&gpio1>; 85 interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 86 87 spi-max-frequency = <1500000>; 88 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; 89 90 ti,x-min = /bits/ 16 <125>; 91 touchscreen-size-x = <4008>; 92 ti,y-min = /bits/ 16 <282>; 93 touchscreen-size-y = <3864>; 94 ti,x-plate-ohms = /bits/ 16 <180>; 95 touchscreen-max-pressure = <255>; 96 touchscreen-average-samples = <10>; 97 ti,debounce-tol = /bits/ 16 <3>; 98 ti,debounce-rep = /bits/ 16 <1>; 99 ti,settle-delay-usec = /bits/ 16 <150>; 100 ti,keep-vref-on; 101 wakeup-source; 102 }; 103}; 104 105&fec1 { 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_fec1>; 108 phy-mode = "rgmii"; 109 phy-handle = <ðphy>; 110 phy-supply = <®_eth_phy>; 111 fsl,magic-packet; 112 status = "okay"; 113 114 mdio { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 118 ethphy: ethernet-phy@4 { 119 compatible = "ethernet-phy-ieee802.3-c22"; 120 reg = <4>; 121 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 122 reset-assert-us = <10000>; 123 reset-deassert-us = <10000>; 124 }; 125 }; 126}; 127 128&i2c1 { 129 clock-frequency = <400000>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_i2c1>; 132 status = "okay"; 133 134 pmic@4b { 135 compatible = "rohm,bd71847"; 136 reg = <0x4b>; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_pmic>; 139 interrupt-parent = <&gpio2>; 140 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 141 rohm,reset-snvs-powered; 142 143 #clock-cells = <0>; 144 clocks = <&osc_32k>; 145 clock-output-names = "clk-32k-out"; 146 147 regulators { 148 buck1_reg: BUCK1 { 149 regulator-name = "buck1"; 150 regulator-min-microvolt = <700000>; 151 regulator-max-microvolt = <1300000>; 152 regulator-boot-on; 153 regulator-always-on; 154 regulator-ramp-delay = <1250>; 155 }; 156 157 buck2_reg: BUCK2 { 158 regulator-name = "buck2"; 159 regulator-min-microvolt = <700000>; 160 regulator-max-microvolt = <1300000>; 161 regulator-boot-on; 162 regulator-always-on; 163 regulator-ramp-delay = <1250>; 164 rohm,dvs-run-voltage = <1000000>; 165 rohm,dvs-idle-voltage = <900000>; 166 }; 167 168 buck3_reg: BUCK3 { 169 regulator-name = "buck3"; 170 regulator-min-microvolt = <700000>; 171 regulator-max-microvolt = <1350000>; 172 regulator-boot-on; 173 regulator-always-on; 174 }; 175 176 buck4_reg: BUCK4 { 177 regulator-name = "buck4"; 178 regulator-min-microvolt = <3000000>; 179 regulator-max-microvolt = <3300000>; 180 regulator-boot-on; 181 regulator-always-on; 182 }; 183 184 buck5_reg: BUCK5 { 185 regulator-name = "buck5"; 186 regulator-min-microvolt = <1605000>; 187 regulator-max-microvolt = <1995000>; 188 regulator-boot-on; 189 regulator-always-on; 190 }; 191 192 buck6_reg: BUCK6 { 193 regulator-name = "buck6"; 194 regulator-min-microvolt = <800000>; 195 regulator-max-microvolt = <1400000>; 196 regulator-boot-on; 197 regulator-always-on; 198 }; 199 200 ldo1_reg: LDO1 { 201 regulator-name = "ldo1"; 202 regulator-min-microvolt = <1600000>; 203 regulator-max-microvolt = <1900000>; 204 regulator-boot-on; 205 regulator-always-on; 206 }; 207 208 ldo2_reg: LDO2 { 209 regulator-name = "ldo2"; 210 regulator-min-microvolt = <800000>; 211 regulator-max-microvolt = <900000>; 212 regulator-boot-on; 213 regulator-always-on; 214 }; 215 216 ldo3_reg: LDO3 { 217 regulator-name = "ldo3"; 218 regulator-min-microvolt = <1800000>; 219 regulator-max-microvolt = <3300000>; 220 regulator-boot-on; 221 regulator-always-on; 222 }; 223 224 ldo4_reg: LDO4 { 225 regulator-name = "ldo4"; 226 regulator-min-microvolt = <900000>; 227 regulator-max-microvolt = <1800000>; 228 regulator-boot-on; 229 regulator-always-on; 230 }; 231 232 ldo5_reg: LDO5 { 233 regulator-min-microvolt = <1800000>; 234 regulator-max-microvolt = <1800000>; 235 regulator-always-on; 236 }; 237 238 ldo6_reg: LDO6 { 239 regulator-name = "ldo6"; 240 regulator-min-microvolt = <900000>; 241 regulator-max-microvolt = <1800000>; 242 regulator-boot-on; 243 regulator-always-on; 244 }; 245 }; 246 }; 247}; 248 249&i2c3 { 250 clock-frequency = <400000>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_i2c3>; 253 status = "okay"; 254 255 /* TODO: configure audio, as of now just put a placeholder */ 256 wm8904: codec@1a { 257 compatible = "wlf,wm8904"; 258 reg = <0x1a>; 259 status = "disabled"; 260 }; 261}; 262 263&snvs_pwrkey { 264 status = "okay"; 265}; 266 267/* Bluetooth */ 268&uart2 { 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_uart2>; 271 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 272 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 273 uart-has-rtscts; 274 status = "okay"; 275}; 276 277/* Console */ 278&uart4 { 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_uart4>; 281 status = "okay"; 282}; 283 284&usbotg1 { 285 dr_mode = "otg"; 286 usb-role-switch; 287 status = "okay"; 288}; 289 290&usbotg2 { 291 dr_mode = "otg"; 292 usb-role-switch; 293 status = "okay"; 294}; 295 296/* WIFI */ 297&usdhc1 { 298 #address-cells = <1>; 299 #size-cells = <0>; 300 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 301 pinctrl-0 = <&pinctrl_usdhc1>; 302 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 303 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 304 bus-width = <4>; 305 non-removable; 306 keep-power-in-suspend; 307 status = "okay"; 308 309 brcmf: bcrmf@1 { 310 reg = <1>; 311 compatible = "brcm,bcm4329-fmac"; 312 }; 313}; 314 315/* SD */ 316&usdhc2 { 317 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 318 assigned-clock-rates = <200000000>; 319 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 320 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 321 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 322 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 323 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 324 bus-width = <4>; 325 vmmc-supply = <®_usdhc2_vmmc>; 326 status = "okay"; 327}; 328 329/* eMMC */ 330&usdhc3 { 331 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 332 assigned-clock-rates = <400000000>; 333 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 334 pinctrl-0 = <&pinctrl_usdhc3>; 335 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 336 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 337 bus-width = <8>; 338 non-removable; 339 status = "okay"; 340}; 341 342&wdog1 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_wdog>; 345 fsl,ext-reset-output; 346 status = "okay"; 347}; 348 349&iomuxc { 350 pinctrl_ecspi1: ecspi1grp { 351 fsl,pins = < 352 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 353 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 354 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 355 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13 356 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13 357 >; 358 }; 359 360 pinctrl_fec1: fec1grp { 361 fsl,pins = < 362 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 363 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 364 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 365 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 366 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 367 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 368 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 369 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 370 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 371 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 372 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 373 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 374 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 375 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 376 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 377 >; 378 }; 379 380 pinctrl_i2c1: i2c1grp { 381 fsl,pins = < 382 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 383 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 384 >; 385 }; 386 387 pinctrl_i2c3: i2c3grp { 388 fsl,pins = < 389 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 390 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 391 >; 392 }; 393 394 pinctrl_pmic: pmicirqgrp { 395 fsl,pins = < 396 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 397 >; 398 }; 399 400 pinctrl_reg_eth_phy: regethphygrp { 401 fsl,pins = < 402 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 403 >; 404 }; 405 406 pinctrl_restouch: restouchgrp { 407 fsl,pins = < 408 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 409 >; 410 }; 411 412 pinctrl_uart2: uart2grp { 413 fsl,pins = < 414 MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 415 MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 416 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 417 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 418 >; 419 }; 420 421 pinctrl_uart4: uart4grp { 422 fsl,pins = < 423 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 424 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 425 >; 426 }; 427 428 pinctrl_usdhc1: usdhc1grp { 429 fsl,pins = < 430 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 431 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 432 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 433 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 434 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 435 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 436 >; 437 }; 438 439 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 440 fsl,pins = < 441 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 442 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 443 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 444 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 445 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 446 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 447 >; 448 }; 449 450 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 451 fsl,pins = < 452 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 453 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 454 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 455 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 456 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 457 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 458 >; 459 }; 460 461 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 462 fsl,pins = < 463 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 464 >; 465 }; 466 467 pinctrl_usdhc2: usdhc2grp { 468 fsl,pins = < 469 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 470 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 471 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 472 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 473 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 474 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 475 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 476 >; 477 }; 478 479 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 480 fsl,pins = < 481 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 482 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 483 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 484 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 485 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 486 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 487 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 488 >; 489 }; 490 491 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 492 fsl,pins = < 493 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 494 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 495 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 496 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 497 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 498 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 499 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 500 >; 501 }; 502 503 pinctrl_usdhc3: usdhc3grp { 504 fsl,pins = < 505 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 506 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 507 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 508 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 509 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 510 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 511 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 512 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 513 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 514 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 515 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 516 >; 517 }; 518 519 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 520 fsl,pins = < 521 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 522 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 523 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 524 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 525 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 526 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 527 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 528 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 529 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 530 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 531 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 532 >; 533 }; 534 535 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 536 fsl,pins = < 537 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 538 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 539 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 540 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 541 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 542 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 543 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 544 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 545 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 546 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 547 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 548 >; 549 }; 550 551 pinctrl_wdog: wdoggrp { 552 fsl,pins = < 553 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 554 >; 555 }; 556}; 557