1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// 3// Copyright 2018 CompuLab 4 5/dts-v1/; 6 7#include "imx8mm.dtsi" 8#include <dt-bindings/leds/common.h> 9 10/ { 11 aliases { 12 rtc0 = &rtc_i2c; 13 rtc1 = &snvs_rtc; 14 mmc0 = &usdhc3; 15 }; 16 17 chosen { 18 stdout-path = &uart3; 19 }; 20 21 backlight { 22 compatible = "pwm-backlight"; 23 pwms = <&pwm2 0 3000000 0>; 24 brightness-levels = <0 255>; 25 num-interpolated-steps = <255>; 26 default-brightness-level = <222>; 27 status = "okay"; 28 }; 29 30 leds { 31 compatible = "gpio-leds"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_gpio_led>; 34 35 heartbeat-led { 36 function = LED_FUNCTION_STATUS; 37 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 38 linux,default-trigger = "heartbeat"; 39 }; 40 }; 41 42 pmic_osc: clock-pmic { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <32768>; 46 clock-output-names = "pmic_osc"; 47 }; 48 49 wlreg_on: regulator-wlreg-on { 50 compatible = "regulator-fixed"; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; 53 regulator-name = "wlreg_on"; 54 gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; 55 startup-delay-us = <100>; 56 enable-active-high; 57 regulator-always-on; 58 status = "okay"; 59 }; 60 61 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 62 compatible = "regulator-fixed"; 63 regulator-name = "VSD_3V3"; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 67 enable-active-high; 68 startup-delay-us = <100>; 69 off-on-delay-us = <12000>; 70 }; 71 72 regulator-usdhc3rst { 73 compatible = "regulator-fixed"; 74 regulator-name = "usdhc3_rst"; 75 regulator-min-microvolt = <3300000>; 76 regulator-max-microvolt = <3300000>; 77 gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; 78 regulator-always-on; 79 enable-active-high; 80 }; 81 82 regulator-fec1rst { 83 compatible = "regulator-fixed"; 84 regulator-name = "fec1_rst"; 85 regulator-min-microvolt = <3300000>; 86 regulator-max-microvolt = <3300000>; 87 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; 88 regulator-always-on; 89 enable-active-high; 90 startup-delay-us = <500>; 91 regulator-boot-on; 92 }; 93}; 94 95&A53_0 { 96 arm-supply = <&buck2>; 97}; 98 99&cpu_alert0 { 100 temperature = <105000>; 101}; 102 103&cpu_crit0 { 104 temperature = <115000>; 105}; 106 107&fec1 { 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_fec1>; 110 phy-mode = "rgmii-id"; 111 phy-handle = <ðphy0>; 112 fsl,magic-packet; 113 status = "okay"; 114 115 mdio { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 ethphy0: ethernet-phy@0 { 120 compatible = "ethernet-phy-ieee802.3-c22"; 121 reg = <0>; 122 }; 123 }; 124}; 125 126&i2c2 { 127 clock-frequency = <400000>; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_i2c2>; 130 status = "okay"; 131 132 pmic@4b { 133 reg = <0x4b>; 134 compatible = "rohm,bd71837"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_pmic>; 137 #clock-cells = <0>; 138 clocks = <&pmic_osc>; 139 clock-names = "osc"; 140 clock-output-names = "pmic_clk"; 141 interrupt-parent = <&gpio1>; 142 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 143 rohm,reset-snvs-powered; 144 145 regulators { 146 buck1: BUCK1 { 147 regulator-name = "buck1"; 148 regulator-min-microvolt = <700000>; 149 regulator-max-microvolt = <1300000>; 150 regulator-boot-on; 151 regulator-always-on; 152 regulator-ramp-delay = <1250>; 153 }; 154 155 buck2: BUCK2 { 156 regulator-name = "buck2"; 157 regulator-min-microvolt = <700000>; 158 regulator-max-microvolt = <1300000>; 159 regulator-boot-on; 160 regulator-always-on; 161 regulator-ramp-delay = <1250>; 162 rohm,dvs-run-voltage = <1000000>; 163 rohm,dvs-idle-voltage = <900000>; 164 }; 165 166 buck3: BUCK3 { 167 regulator-name = "buck3"; 168 regulator-min-microvolt = <700000>; 169 regulator-max-microvolt = <1300000>; 170 regulator-boot-on; 171 regulator-always-on; 172 }; 173 174 buck4: BUCK4 { 175 regulator-name = "buck4"; 176 regulator-min-microvolt = <700000>; 177 regulator-max-microvolt = <1300000>; 178 regulator-boot-on; 179 regulator-always-on; 180 }; 181 182 buck5: BUCK5 { 183 regulator-name = "buck5"; 184 regulator-min-microvolt = <700000>; 185 regulator-max-microvolt = <1350000>; 186 regulator-boot-on; 187 regulator-always-on; 188 }; 189 190 buck6: BUCK6 { 191 regulator-name = "buck6"; 192 regulator-min-microvolt = <3000000>; 193 regulator-max-microvolt = <3300000>; 194 regulator-boot-on; 195 regulator-always-on; 196 }; 197 198 buck7: BUCK7 { 199 regulator-name = "buck7"; 200 regulator-min-microvolt = <1605000>; 201 regulator-max-microvolt = <1995000>; 202 regulator-boot-on; 203 regulator-always-on; 204 }; 205 206 buck8: BUCK8 { 207 regulator-name = "buck8"; 208 regulator-min-microvolt = <800000>; 209 regulator-max-microvolt = <1400000>; 210 regulator-boot-on; 211 regulator-always-on; 212 }; 213 214 ldo1: LDO1 { 215 regulator-name = "ldo1"; 216 regulator-min-microvolt = <1600000>; 217 regulator-max-microvolt = <1900000>; 218 regulator-boot-on; 219 regulator-always-on; 220 }; 221 222 ldo2: LDO2 { 223 regulator-name = "ldo2"; 224 regulator-min-microvolt = <800000>; 225 regulator-max-microvolt = <900000>; 226 regulator-boot-on; 227 regulator-always-on; 228 }; 229 230 ldo3: LDO3 { 231 regulator-name = "ldo3"; 232 regulator-min-microvolt = <1800000>; 233 regulator-max-microvolt = <3300000>; 234 regulator-boot-on; 235 regulator-always-on; 236 }; 237 238 ldo4: LDO4 { 239 regulator-name = "ldo4"; 240 regulator-min-microvolt = <900000>; 241 regulator-max-microvolt = <1800000>; 242 regulator-boot-on; 243 regulator-always-on; 244 }; 245 246 ldo5: LDO5 { 247 regulator-name = "ldo5"; 248 regulator-min-microvolt = <1800000>; 249 regulator-max-microvolt = <3300000>; 250 }; 251 252 ldo6: LDO6 { 253 regulator-name = "ldo6"; 254 regulator-min-microvolt = <900000>; 255 regulator-max-microvolt = <1800000>; 256 regulator-boot-on; 257 regulator-always-on; 258 }; 259 260 ldo7: LDO7 { 261 regulator-name = "ldo7"; 262 regulator-min-microvolt = <1800000>; 263 regulator-max-microvolt = <3300000>; 264 }; 265 }; 266 }; 267 268 eeprom@50 { 269 compatible = "atmel,24c08"; 270 reg = <0x50>; 271 pagesize = <16>; 272 }; 273 274 rtc_i2c: rtc@69 { 275 compatible = "abracon,ab1805"; 276 reg = <0x69>; 277 }; 278}; 279 280&i2c3 { 281 clock-frequency = <100000>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_i2c3>; 284 status = "disabled"; 285}; 286 287&pwm2 { 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_pwm_backlight>; 290 status = "okay"; 291}; 292 293&sai2 { 294 #sound-dai-cells = <0>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_sai2>; 297 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 298 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 299 assigned-clock-rates = <49152000>; 300 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>, 301 <&clk IMX8MM_CLK_SAI2_ROOT>, <&clk IMX8MM_CLK_DUMMY>, 302 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, 303 <&clk IMX8MM_AUDIO_PLL2_OUT>; 304 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 305 fsl,sai-asynchronous; 306 status = "okay"; 307}; 308 309&snvs { 310 status = "okay"; 311}; 312 313&snvs_pwrkey { 314 status = "okay"; 315}; 316 317&uart1 { 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_uart1>; 320 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 321 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 322 status = "disabled"; 323}; 324 325&uart2 { 326 pinctrl-names = "default"; 327 pinctrl-0 = <&pinctrl_uart2>; 328 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 329 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 330 status = "disabled"; 331}; 332 333&uart3 { /* console */ 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_uart3>; 336 status = "okay"; 337}; 338 339&uart4 { /* bluetooth */ 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_uart4>; 342 assigned-clocks = <&clk IMX8MM_CLK_UART4>; 343 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 344 uart-has-rtscts; 345 status = "disabled"; 346 347 bluetooth { 348 compatible = "brcm,bcm4330-bt"; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_bt>; 351 max-speed = <3000000>; 352 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 353 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 354 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 355 }; 356}; 357 358&usbotg1 { 359 dr_mode = "otg"; 360 hnp-disable; 361 srp-disable; 362 disable-over-current; 363 status = "disabled"; 364}; 365 366&usbotg2 { 367 dr_mode = "host"; 368 hnp-disable; 369 srp-disable; 370 disable-over-current; 371 status = "disabled"; 372}; 373 374&usdhc1 { 375 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 376 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 377 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 378 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 379 bus-width = <4>; 380 non-removable; 381}; 382 383&usdhc2 { 384 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 385 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 386 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 387 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 388 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 389 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 390 no-1-8-v; 391 bus-width = <4>; 392 vmmc-supply = <®_usdhc2_vmmc>; 393 status = "okay"; 394}; 395 396&usdhc3 { 397 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 398 pinctrl-0 = <&pinctrl_usdhc3>; 399 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 400 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 401 bus-width = <8>; 402 non-removable; 403 no-1-8-v; 404 status = "okay"; 405}; 406 407&wdog1 { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_wdog>; 410 fsl,ext-reset-output; 411 status = "okay"; 412}; 413 414&iomuxc { 415 pinctrl-names = "default"; 416 pinctrl-0 = <&pinctrl_hog_1>; 417 418 pinctrl_hog: hoggrp { 419 fsl,pins = < 420 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 421 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x190 422 >; 423 }; 424 425 pinctrl_bt: bt0grp { 426 fsl,pins = < 427 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 /* BT_REG_ON */ 428 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 /* BT_DEV_WU */ 429 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 /* BT_HST_WU */ 430 >; 431 }; 432 433 pinctrl_fec1: fec1grp { 434 fsl,pins = < 435 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 436 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 437 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 438 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 439 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 440 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 441 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 442 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 443 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 444 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 445 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 446 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 447 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 448 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 449 >; 450 }; 451 452 pinctrl_gpio_led: gpioledgrp { 453 fsl,pins = < 454 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 455 >; 456 }; 457 458 pinctrl_i2c1: i2c1grp { 459 fsl,pins = < 460 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 461 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 462 >; 463 }; 464 465 pinctrl_i2c2: i2c2grp { 466 fsl,pins = < 467 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 468 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 469 >; 470 }; 471 472 pinctrl_i2c3: i2c3grp { 473 fsl,pins = < 474 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 475 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 476 >; 477 }; 478 479 pinctrl_i2c4: i2c4grp { 480 fsl,pins = < 481 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 482 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 483 >; 484 }; 485 486 pinctrl_pmic: pmicgrp { 487 fsl,pins = < 488 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 489 >; 490 }; 491 492 pinctrl_pwm_backlight: pwmbacklightgrp { 493 fsl,pins = < 494 MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x03 495 >; 496 }; 497 498 499 pinctrl_sai2: sai2grp { 500 fsl,pins = < 501 MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 502 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 503 MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 504 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 505 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 506 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 507 >; 508 }; 509 510 pinctrl_uart1: uart1grp { 511 fsl,pins = < 512 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 513 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 514 >; 515 }; 516 517 pinctrl_uart2: uart2grp { 518 fsl,pins = < 519 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 520 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 521 >; 522 }; 523 524 pinctrl_uart3: uart3grp { 525 fsl,pins = < 526 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 527 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 528 >; 529 }; 530 531 pinctrl_uart4: uart4grp { 532 fsl,pins = < 533 MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140 534 MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140 535 MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140 536 MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140 537 >; 538 }; 539 540 pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { 541 fsl,pins = < 542 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 543 >; 544 }; 545 546 pinctrl_usdhc1: usdhc1grp { 547 fsl,pins = < 548 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 549 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 550 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 551 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 552 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 553 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 554 MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0 555 >; 556 }; 557 558 pinctrl_usdhc1_100mhz: usdhc1grp100mhzgrp { 559 fsl,pins = < 560 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 561 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 562 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 563 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 564 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 565 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 566 MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0 567 >; 568 }; 569 570 pinctrl_usdhc1_200mhz: usdhc1grp200mhzgrp { 571 fsl,pins = < 572 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 573 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 574 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 575 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 576 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 577 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 578 MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0 579 >; 580 }; 581 582 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { 583 fsl,pins = < 584 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 585 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 586 MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x00 587 >; 588 }; 589 590 pinctrl_usdhc2: usdhc2grp { 591 fsl,pins = < 592 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 593 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 594 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 595 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 596 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 597 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 598 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 599 >; 600 }; 601 602 pinctrl_usdhc2_100mhz: usdhc2grp100mhzgrp { 603 fsl,pins = < 604 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 605 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 606 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 607 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 608 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 609 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 610 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 611 >; 612 }; 613 614 pinctrl_usdhc2_200mhz: usdhc2grp200mhzgrp { 615 fsl,pins = < 616 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 617 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 618 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 619 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 620 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 621 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 622 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 623 >; 624 }; 625 626 pinctrl_usdhc3: usdhc3grp { 627 fsl,pins = < 628 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 629 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 630 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 631 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 632 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 633 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 634 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 635 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 636 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 637 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 638 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 639 >; 640 }; 641 642 pinctrl_usdhc3_100mhz: usdhc3grp100mhzgrp { 643 fsl,pins = < 644 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 645 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 646 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 647 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 648 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 649 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 650 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 651 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 652 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 653 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 654 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 655 >; 656 }; 657 658 pinctrl_usdhc3_200mhz: usdhc3grp200mhzgrp { 659 fsl,pins = < 660 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 661 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 662 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 663 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 664 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 665 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 666 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 667 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 668 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 669 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 670 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 671 >; 672 }; 673 674 pinctrl_wdog: wdoggrp { 675 fsl,pins = < 676 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 677 >; 678 }; 679}; 680