1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright 2020-2021 TQ-Systems GmbH 4 */ 5 6#include "imx8mm.dtsi" 7 8/ { 9 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML"; 10 compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; 11 12 memory@40000000 { 13 device_type = "memory"; 14 /* our minimum RAM config will be 1024 MiB */ 15 reg = <0x00000000 0x40000000 0 0x40000000>; 16 }; 17 18 /* e-MMC IO, needed for HS modes */ 19 reg_vcc1v8: regulator-vcc1v8 { 20 compatible = "regulator-fixed"; 21 regulator-name = "TQMA8MXML_VCC1V8"; 22 regulator-min-microvolt = <1800000>; 23 regulator-max-microvolt = <1800000>; 24 }; 25 26 /* identical to buck4_reg, but should never change */ 27 reg_vcc3v3: regulator-vcc3v3 { 28 compatible = "regulator-fixed"; 29 regulator-name = "TQMA8MXML_VCC3V3"; 30 regulator-min-microvolt = <3300000>; 31 regulator-max-microvolt = <3300000>; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 /* global autoconfigured region for contiguous allocations */ 40 linux,cma { 41 compatible = "shared-dma-pool"; 42 reusable; 43 /* 640 MiB */ 44 size = <0 0x28000000>; 45 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ 46 alloc-ranges = <0 0x40000000 0 0x78000000>; 47 linux,cma-default; 48 }; 49 }; 50}; 51 52&A53_0 { 53 cpu-supply = <&buck2_reg>; 54}; 55 56&flexspi { 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_flexspi>; 59 status = "okay"; 60 61 flash0: flash@0 { 62 compatible = "jedec,spi-nor"; 63 reg = <0>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 spi-max-frequency = <84000000>; 67 spi-tx-bus-width = <1>; 68 spi-rx-bus-width = <4>; 69 }; 70}; 71 72&gpu_2d { 73 status = "okay"; 74}; 75 76&gpu_3d { 77 status = "okay"; 78}; 79 80&i2c1 { 81 clock-frequency = <100000>; 82 pinctrl-names = "default", "gpio"; 83 pinctrl-0 = <&pinctrl_i2c1>; 84 pinctrl-1 = <&pinctrl_i2c1_gpio>; 85 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 86 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 87 status = "okay"; 88 89 sensor0: temperature-sensor-eeprom@1b { 90 compatible = "nxp,se97", "jedec,jc-42.4-temp"; 91 reg = <0x1b>; 92 }; 93 94 pca9450: pmic@25 { 95 compatible = "nxp,pca9450a"; 96 reg = <0x25>; 97 98 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ 99 pinctrl-0 = <&pinctrl_pmic>; 100 pinctrl-names = "default"; 101 interrupt-parent = <&gpio1>; 102 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 103 104 regulators { 105 /* V_0V85_SOC: 0.85 */ 106 buck1_reg: BUCK1 { 107 regulator-name = "BUCK1"; 108 regulator-min-microvolt = <850000>; 109 regulator-max-microvolt = <850000>; 110 regulator-boot-on; 111 regulator-always-on; 112 regulator-ramp-delay = <3125>; 113 }; 114 115 /* VDD_ARM */ 116 buck2_reg: BUCK2 { 117 regulator-name = "BUCK2"; 118 regulator-min-microvolt = <850000>; 119 regulator-max-microvolt = <1000000>; 120 regulator-boot-on; 121 regulator-always-on; 122 nxp,dvs-run-voltage = <950000>; 123 nxp,dvs-standby-voltage = <850000>; 124 regulator-ramp-delay = <3125>; 125 }; 126 127 /* V_0V85_GPU / DRAM / VPU */ 128 buck3_reg: BUCK3 { 129 regulator-name = "BUCK3"; 130 regulator-min-microvolt = <850000>; 131 regulator-max-microvolt = <950000>; 132 regulator-boot-on; 133 regulator-always-on; 134 regulator-ramp-delay = <3125>; 135 }; 136 137 /* VCC3V3 -> VMMC, ... must not be changed */ 138 buck4_reg: BUCK4 { 139 regulator-name = "BUCK4"; 140 regulator-min-microvolt = <3300000>; 141 regulator-max-microvolt = <3300000>; 142 regulator-boot-on; 143 regulator-always-on; 144 }; 145 146 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ 147 buck5_reg: BUCK5 { 148 regulator-name = "BUCK5"; 149 regulator-min-microvolt = <1800000>; 150 regulator-max-microvolt = <1800000>; 151 regulator-boot-on; 152 regulator-always-on; 153 }; 154 155 /* V_1V1 -> RAM, ... must not be changed */ 156 buck6_reg: BUCK6 { 157 regulator-name = "BUCK6"; 158 regulator-min-microvolt = <1100000>; 159 regulator-max-microvolt = <1100000>; 160 regulator-boot-on; 161 regulator-always-on; 162 }; 163 164 /* V_1V8_SNVS */ 165 ldo1_reg: LDO1 { 166 regulator-name = "LDO1"; 167 regulator-min-microvolt = <1800000>; 168 regulator-max-microvolt = <1800000>; 169 regulator-boot-on; 170 regulator-always-on; 171 }; 172 173 /* V_0V8_SNVS */ 174 ldo2_reg: LDO2 { 175 regulator-name = "LDO2"; 176 regulator-min-microvolt = <800000>; 177 regulator-max-microvolt = <850000>; 178 regulator-boot-on; 179 regulator-always-on; 180 }; 181 182 /* V_1V8_ANA */ 183 ldo3_reg: LDO3 { 184 regulator-name = "LDO3"; 185 regulator-min-microvolt = <1800000>; 186 regulator-max-microvolt = <1800000>; 187 regulator-boot-on; 188 regulator-always-on; 189 }; 190 191 /* V_0V9_MIPI */ 192 ldo4_reg: LDO4 { 193 regulator-name = "LDO4"; 194 regulator-min-microvolt = <900000>; 195 regulator-max-microvolt = <900000>; 196 regulator-boot-on; 197 regulator-always-on; 198 }; 199 200 /* VCC SD IO - switched using SD2 VSELECT */ 201 ldo5_reg: LDO5 { 202 regulator-name = "LDO5"; 203 regulator-min-microvolt = <1800000>; 204 regulator-max-microvolt = <3300000>; 205 }; 206 }; 207 }; 208 209 210 pcf85063: rtc@51 { 211 compatible = "nxp,pcf85063a"; 212 reg = <0x51>; 213 quartz-load-femtofarads = <7000>; 214 }; 215 216 eeprom1: eeprom@53 { 217 compatible = "nxp,se97b", "atmel,24c02"; 218 read-only; 219 reg = <0x53>; 220 pagesize = <16>; 221 }; 222 223 eeprom0: eeprom@57 { 224 compatible = "atmel,24c64"; 225 reg = <0x57>; 226 pagesize = <32>; 227 }; 228}; 229 230&pcie_phy { 231 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 232 fsl,clkreq-unsupported; 233}; 234 235&usdhc3 { 236 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 237 pinctrl-0 = <&pinctrl_usdhc3>; 238 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 239 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 240 bus-width = <8>; 241 non-removable; 242 no-sd; 243 no-sdio; 244 vmmc-supply = <®_vcc3v3>; 245 vqmmc-supply = <®_vcc1v8>; 246 status = "okay"; 247}; 248 249/* 250 * Attention: 251 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR 252 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. 253 */ 254&wdog1 { 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_wdog>; 257 fsl,ext-reset-output; 258 status = "okay"; 259}; 260 261&iomuxc { 262 pinctrl_flexspi: flexspigrp { 263 fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>, 264 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, 265 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, 266 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, 267 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, 268 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; 269 }; 270 271 pinctrl_i2c1: i2c1grp { 272 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>, 273 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>; 274 }; 275 276 pinctrl_i2c1_gpio: i2c1gpiogrp { 277 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>, 278 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>; 279 }; 280 281 pinctrl_pmic: pmicgrp { 282 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>; 283 }; 284 285 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 286 fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; 287 }; 288 289 pinctrl_usdhc3: usdhc3grp { 290 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, 291 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 292 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 293 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 294 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 295 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 296 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 297 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 298 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 299 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 300 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 301 /* option USDHC3_RESET_B not defined, only in RM */ 302 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; 303 }; 304 305 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 306 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, 307 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 308 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 309 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 310 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 311 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 312 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 313 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 314 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 315 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 316 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 317 /* option USDHC3_RESET_B not defined, only in RM */ 318 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; 319 }; 320 321 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 322 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, 323 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 324 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 325 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 326 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 327 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 328 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 329 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 330 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 331 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 332 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 333 /* option USDHC3_RESET_B not defined, only in RM */ 334 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; 335 }; 336 337 pinctrl_wdog: wdoggrp { 338 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; 339 }; 340}; 341