1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright 2020-2021 TQ-Systems GmbH 4 */ 5 6#include <dt-bindings/phy/phy-imx8-pcie.h> 7#include "imx8mm.dtsi" 8 9/ { 10 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML"; 11 compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; 12 13 memory@40000000 { 14 device_type = "memory"; 15 /* our minimum RAM config will be 1024 MiB */ 16 reg = <0x00000000 0x40000000 0 0x40000000>; 17 }; 18 19 /* e-MMC IO, needed for HS modes */ 20 reg_vcc1v8: regulator-vcc1v8 { 21 compatible = "regulator-fixed"; 22 regulator-name = "TQMA8MXML_VCC1V8"; 23 regulator-min-microvolt = <1800000>; 24 regulator-max-microvolt = <1800000>; 25 }; 26 27 /* identical to buck4_reg, but should never change */ 28 reg_vcc3v3: regulator-vcc3v3 { 29 compatible = "regulator-fixed"; 30 regulator-name = "TQMA8MXML_VCC3V3"; 31 regulator-min-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>; 33 }; 34 35 reserved-memory { 36 #address-cells = <2>; 37 #size-cells = <2>; 38 ranges; 39 40 /* global autoconfigured region for contiguous allocations */ 41 linux,cma { 42 compatible = "shared-dma-pool"; 43 reusable; 44 /* 640 MiB */ 45 size = <0 0x28000000>; 46 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ 47 alloc-ranges = <0 0x40000000 0 0x78000000>; 48 linux,cma-default; 49 }; 50 }; 51}; 52 53&A53_0 { 54 cpu-supply = <&buck2_reg>; 55}; 56 57&flexspi { 58 pinctrl-names = "default"; 59 pinctrl-0 = <&pinctrl_flexspi>; 60 status = "okay"; 61 62 flash0: flash@0 { 63 compatible = "jedec,spi-nor"; 64 reg = <0>; 65 spi-max-frequency = <84000000>; 66 spi-tx-bus-width = <1>; 67 spi-rx-bus-width = <4>; 68 69 partitions { 70 compatible = "fixed-partitions"; 71 #address-cells = <1>; 72 #size-cells = <1>; 73 }; 74 }; 75}; 76 77&gpu_2d { 78 status = "okay"; 79}; 80 81&gpu_3d { 82 status = "okay"; 83}; 84 85&i2c1 { 86 clock-frequency = <100000>; 87 pinctrl-names = "default", "gpio"; 88 pinctrl-0 = <&pinctrl_i2c1>; 89 pinctrl-1 = <&pinctrl_i2c1_gpio>; 90 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 91 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 92 status = "okay"; 93 94 sensor0: temperature-sensor@1b { 95 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 96 reg = <0x1b>; 97 }; 98 99 pca9450: pmic@25 { 100 compatible = "nxp,pca9450a"; 101 reg = <0x25>; 102 103 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ 104 pinctrl-0 = <&pinctrl_pmic>; 105 pinctrl-names = "default"; 106 interrupt-parent = <&gpio1>; 107 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 108 109 regulators { 110 /* V_0V85_SOC: 0.85 */ 111 buck1_reg: BUCK1 { 112 regulator-name = "BUCK1"; 113 regulator-min-microvolt = <850000>; 114 regulator-max-microvolt = <850000>; 115 regulator-boot-on; 116 regulator-always-on; 117 regulator-ramp-delay = <3125>; 118 }; 119 120 /* VDD_ARM */ 121 buck2_reg: BUCK2 { 122 regulator-name = "BUCK2"; 123 regulator-min-microvolt = <850000>; 124 regulator-max-microvolt = <1000000>; 125 regulator-boot-on; 126 regulator-always-on; 127 nxp,dvs-run-voltage = <950000>; 128 nxp,dvs-standby-voltage = <850000>; 129 regulator-ramp-delay = <3125>; 130 }; 131 132 /* V_0V85_GPU / DRAM / VPU */ 133 buck3_reg: BUCK3 { 134 regulator-name = "BUCK3"; 135 regulator-min-microvolt = <850000>; 136 regulator-max-microvolt = <950000>; 137 regulator-boot-on; 138 regulator-always-on; 139 regulator-ramp-delay = <3125>; 140 }; 141 142 /* VCC3V3 -> VMMC, ... must not be changed */ 143 buck4_reg: BUCK4 { 144 regulator-name = "BUCK4"; 145 regulator-min-microvolt = <3300000>; 146 regulator-max-microvolt = <3300000>; 147 regulator-boot-on; 148 regulator-always-on; 149 }; 150 151 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ 152 buck5_reg: BUCK5 { 153 regulator-name = "BUCK5"; 154 regulator-min-microvolt = <1800000>; 155 regulator-max-microvolt = <1800000>; 156 regulator-boot-on; 157 regulator-always-on; 158 }; 159 160 /* V_1V1 -> RAM, ... must not be changed */ 161 buck6_reg: BUCK6 { 162 regulator-name = "BUCK6"; 163 regulator-min-microvolt = <1100000>; 164 regulator-max-microvolt = <1100000>; 165 regulator-boot-on; 166 regulator-always-on; 167 }; 168 169 /* V_1V8_SNVS */ 170 ldo1_reg: LDO1 { 171 regulator-name = "LDO1"; 172 regulator-min-microvolt = <1800000>; 173 regulator-max-microvolt = <1800000>; 174 regulator-boot-on; 175 regulator-always-on; 176 }; 177 178 /* V_0V8_SNVS */ 179 ldo2_reg: LDO2 { 180 regulator-name = "LDO2"; 181 regulator-min-microvolt = <800000>; 182 regulator-max-microvolt = <850000>; 183 regulator-boot-on; 184 regulator-always-on; 185 }; 186 187 /* V_1V8_ANA */ 188 ldo3_reg: LDO3 { 189 regulator-name = "LDO3"; 190 regulator-min-microvolt = <1800000>; 191 regulator-max-microvolt = <1800000>; 192 regulator-boot-on; 193 regulator-always-on; 194 }; 195 196 /* V_0V9_MIPI */ 197 ldo4_reg: LDO4 { 198 regulator-name = "LDO4"; 199 regulator-min-microvolt = <900000>; 200 regulator-max-microvolt = <900000>; 201 regulator-boot-on; 202 regulator-always-on; 203 }; 204 205 /* VCC SD IO - switched using SD2 VSELECT */ 206 ldo5_reg: LDO5 { 207 regulator-name = "LDO5"; 208 regulator-min-microvolt = <1800000>; 209 regulator-max-microvolt = <3300000>; 210 }; 211 }; 212 }; 213 214 215 pcf85063: rtc@51 { 216 compatible = "nxp,pcf85063a"; 217 reg = <0x51>; 218 quartz-load-femtofarads = <7000>; 219 }; 220 221 eeprom1: eeprom@53 { 222 compatible = "nxp,se97b", "atmel,24c02"; 223 read-only; 224 reg = <0x53>; 225 pagesize = <16>; 226 vcc-supply = <®_vcc3v3>; 227 }; 228 229 eeprom0: eeprom@57 { 230 compatible = "atmel,24c64"; 231 reg = <0x57>; 232 pagesize = <32>; 233 vcc-supply = <®_vcc3v3>; 234 }; 235}; 236 237&mipi_dsi { 238 vddcore-supply = <&ldo4_reg>; 239 vddio-supply = <&ldo3_reg>; 240}; 241 242&pcie_phy { 243 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 244 fsl,clkreq-unsupported; 245}; 246 247&usdhc3 { 248 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 249 pinctrl-0 = <&pinctrl_usdhc3>; 250 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 251 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 252 bus-width = <8>; 253 non-removable; 254 no-sd; 255 no-sdio; 256 vmmc-supply = <®_vcc3v3>; 257 vqmmc-supply = <®_vcc1v8>; 258 status = "okay"; 259}; 260 261/* 262 * Attention: 263 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR 264 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. 265 */ 266&wdog1 { 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_wdog>; 269 fsl,ext-reset-output; 270 status = "okay"; 271}; 272 273&iomuxc { 274 pinctrl_flexspi: flexspigrp { 275 fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82>, 276 <MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82>, 277 <MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82>, 278 <MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82>, 279 <MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82>, 280 <MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>; 281 }; 282 283 pinctrl_i2c1: i2c1grp { 284 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000004>, 285 <MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000004>; 286 }; 287 288 pinctrl_i2c1_gpio: i2c1gpiogrp { 289 fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x40000004>, 290 <MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x40000004>; 291 }; 292 293 pinctrl_pmic: pmicgrp { 294 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>; 295 }; 296 297 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 298 fsl,pins = <MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; 299 }; 300 301 pinctrl_usdhc3: usdhc3grp { 302 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, 303 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 304 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 305 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 306 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 307 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 308 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 309 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 310 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 311 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 312 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 313 /* option USDHC3_RESET_B not defined, only in RM */ 314 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; 315 }; 316 317 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 318 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, 319 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 320 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 321 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 322 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 323 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 324 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 325 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 326 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 327 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 328 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 329 /* option USDHC3_RESET_B not defined, only in RM */ 330 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; 331 }; 332 333 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 334 fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, 335 <MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 336 <MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 337 <MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 338 <MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 339 <MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 340 <MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 341 <MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 342 <MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 343 <MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 344 <MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 345 /* option USDHC3_RESET_B not defined, only in RM */ 346 <MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x84>; 347 }; 348 349 pinctrl_wdog: wdoggrp { 350 fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; 351 }; 352}; 353