xref: /linux/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts (revision da1d9caf95def6f0320819cf941c9fd1069ba9e1) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright 2020-2021 TQ-Systems GmbH
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9#include "imx8mm-tqma8mqml.dtsi"
10#include "mba8mx.dtsi"
11
12/ {
13	model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
14	compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
15
16	aliases {
17		eeprom0 = &eeprom3;
18		mmc0 = &usdhc3;
19		mmc1 = &usdhc2;
20		mmc2 = &usdhc1;
21		rtc0 = &pcf85063;
22		rtc1 = &snvs_rtc;
23	};
24
25	reg_usdhc2_vmmc: regulator-vmmc {
26		compatible = "regulator-fixed";
27		pinctrl-names = "default";
28		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
29		regulator-name = "VSD_3V3";
30		regulator-min-microvolt = <3300000>;
31		regulator-max-microvolt = <3300000>;
32		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
33		enable-active-high;
34		startup-delay-us = <100>;
35		off-on-delay-us = <12000>;
36	};
37
38	extcon_usbotg1: extcon-usbotg1 {
39		compatible = "linux,extcon-usb-gpio";
40		pinctrl-names = "default";
41		pinctrl-0 = <&pinctrl_usb1_extcon>;
42		id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
43	};
44};
45
46&i2c1 {
47	expander2: gpio@27 {
48		compatible = "nxp,pca9555";
49		reg = <0x27>;
50		gpio-controller;
51		#gpio-cells = <2>;
52		vcc-supply = <&reg_vcc_3v3>;
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_expander>;
55		interrupt-parent = <&gpio1>;
56		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
57		interrupt-controller;
58		#interrupt-cells = <2>;
59	};
60};
61
62&pcie_phy {
63	clocks = <&pcie0_refclk>;
64	status = "okay";
65};
66
67&pcie0 {
68	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
69	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
70		<&pcie0_refclk>;
71	clock-names = "pcie", "pcie_aux", "pcie_bus";
72	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
73				<&clk IMX8MM_CLK_PCIE1_CTRL>;
74	assigned-clock-rates = <10000000>, <250000000>;
75	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
76				<&clk IMX8MM_SYS_PLL2_250M>;
77	status = "okay";
78};
79
80&sai3 {
81	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
82	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
83	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
84	clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
85		<&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
86		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
87		<&clk IMX8MM_AUDIO_PLL2_OUT>;
88};
89
90&tlv320aic3x04 {
91	clock-names = "mclk";
92	clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
93};
94
95&uart1 {
96	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
97	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
98};
99
100&uart2 {
101	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
102	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
103};
104
105&usbotg1 {
106	pinctrl-names = "default";
107	pinctrl-0 = <&pinctrl_usbotg1>;
108	dr_mode = "otg";
109	extcon = <&extcon_usbotg1>;
110	srp-disable;
111	hnp-disable;
112	adp-disable;
113	power-active-high;
114	over-current-active-low;
115	status = "okay";
116};
117
118&usbotg2 {
119	dr_mode = "host";
120	disable-over-current;
121	vbus-supply = <&reg_hub_vbus>;
122	status = "okay";
123};
124
125&iomuxc {
126	pinctrl_ecspi1: ecspi1grp {
127		fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x00000006>,
128			   <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x00000006>,
129			   <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x00000006>,
130			   <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x00000006>;
131	};
132
133	pinctrl_ecspi2: ecspi2grp {
134		fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x00000006>,
135			   <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x00000006>,
136			   <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x00000006>,
137			   <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x00000006>;
138	};
139
140	pinctrl_expander: expandergrp {
141		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x94>;
142	};
143
144	pinctrl_fec1: fec1grp {
145		fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002>,
146			   <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002>,
147			   <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x14>,
148			   <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x14>,
149			   <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x14>,
150			   <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x14>,
151			   <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x90>,
152			   <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x90>,
153			   <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x90>,
154			   <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x90>,
155			   <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x14>,
156			   <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x90>,
157			   <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90>,
158			   <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14>;
159	};
160
161	pinctrl_gpiobutton: gpiobuttongrp {
162		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x84>,
163			   <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x84>,
164			   <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x84>;
165	};
166
167	pinctrl_gpioled: gpioledgrp {
168		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x84>,
169			   <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14		0x84>;
170	};
171
172	pinctrl_i2c2: i2c2grp {
173		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000004>,
174			   <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000004>;
175	};
176
177	pinctrl_i2c2_gpio: i2c2gpiogrp {
178		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000004>,
179			   <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000004>;
180	};
181
182	pinctrl_i2c3: i2c3grp {
183		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000004>,
184			   <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000004>;
185	};
186
187	pinctrl_i2c3_gpio: i2c3gpiogrp {
188		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000004>,
189			   <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000004>;
190	};
191
192	pinctrl_pwm3: pwm3grp {
193		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT		0x14>;
194	};
195
196	pinctrl_pwm4: pwm4grp {
197		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT		0x14>;
198	};
199
200	pinctrl_sai3: sai3grp {
201		fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0x94>,
202			   <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0x94>,
203			   <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0x94>,
204			   <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0x94>,
205			   <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0x94>,
206			   <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0x94>,
207			   <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0x94>;
208	};
209
210	pinctrl_uart1: uart1grp {
211		fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x16>,
212			   <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x16>;
213	};
214
215	pinctrl_uart2: uart2grp {
216		fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x16>,
217			   <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x16>;
218	};
219
220	pinctrl_uart3: uart3grp {
221		fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x16>,
222			   <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x16>;
223	};
224
225	pinctrl_uart4: uart4grp {
226		fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x16>,
227			   <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x16>;
228	};
229
230	pinctrl_usbotg1: usbotg1grp {
231		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x84>,
232			   <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x84>;
233	};
234
235	pinctrl_usb1_extcon: usb1-extcongrp {
236		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c0>;
237	};
238
239	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
240		fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x84>;
241	};
242
243	pinctrl_usdhc2: usdhc2grp {
244		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
245			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
246			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
247			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
248			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
249			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
250			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
251	};
252
253	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
254		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
255			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
256			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
257			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
258			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
259			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
260			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
261	};
262
263	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
264		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
265			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
266			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
267			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
268			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
269			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
270			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
271	};
272};
273