xref: /linux/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Copyright 2020-2021 TQ-Systems GmbH
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy-imx8-pcie.h>
9
10#include "imx8mm-tqma8mqml.dtsi"
11#include "mba8mx.dtsi"
12
13/ {
14	model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
15	compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
16	chassis-type = "embedded";
17
18	aliases {
19		eeprom0 = &eeprom3;
20		mmc0 = &usdhc3;
21		mmc1 = &usdhc2;
22		mmc2 = &usdhc1;
23		rtc0 = &pcf85063;
24		rtc1 = &snvs_rtc;
25	};
26
27	reg_usdhc2_vmmc: regulator-vmmc {
28		compatible = "regulator-fixed";
29		pinctrl-names = "default";
30		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
31		regulator-name = "VSD_3V3";
32		regulator-min-microvolt = <3300000>;
33		regulator-max-microvolt = <3300000>;
34		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
35		enable-active-high;
36		startup-delay-us = <100>;
37		off-on-delay-us = <12000>;
38	};
39
40	connector {
41		compatible = "gpio-usb-b-connector", "usb-b-connector";
42		type = "micro";
43		label = "X19";
44		pinctrl-names = "default";
45		pinctrl-0 = <&pinctrl_usb1_connector>;
46		id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
47
48		ports {
49			#address-cells = <1>;
50			#size-cells = <0>;
51
52			port@0 {
53				reg = <0>;
54				usb_dr_connector: endpoint {
55					remote-endpoint = <&usb1_drd_sw>;
56				};
57			};
58		};
59	};
60};
61
62&i2c1 {
63	expander2: gpio@27 {
64		compatible = "nxp,pca9555";
65		reg = <0x27>;
66		gpio-controller;
67		#gpio-cells = <2>;
68		vcc-supply = <&reg_vcc_3v3>;
69		pinctrl-names = "default";
70		pinctrl-0 = <&pinctrl_expander>;
71		interrupt-parent = <&gpio1>;
72		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
73		interrupt-controller;
74		#interrupt-cells = <2>;
75	};
76};
77
78&pcie_phy {
79	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
80	fsl,clkreq-unsupported;
81	clocks = <&pcieclk 2>;
82	clock-names = "ref";
83	status = "okay";
84};
85
86/* PCIe slot on X36 */
87&pcie0 {
88	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
89	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcieclk 3>,
90		 <&clk IMX8MM_CLK_PCIE1_AUX>;
91	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
92			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
93	assigned-clock-rates = <10000000>, <250000000>;
94	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
95				 <&clk IMX8MM_SYS_PLL2_250M>;
96	status = "okay";
97};
98
99&sai3 {
100	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
101	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
102	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
103	clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
104		<&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
105		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
106		<&clk IMX8MM_AUDIO_PLL2_OUT>;
107};
108
109&tlv320aic3x04 {
110	clock-names = "mclk";
111	clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
112};
113
114&uart1 {
115	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
116	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
117};
118
119&uart2 {
120	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
121	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
122};
123
124&usbotg1 {
125	pinctrl-names = "default";
126	pinctrl-0 = <&pinctrl_usbotg1>;
127	dr_mode = "otg";
128	srp-disable;
129	hnp-disable;
130	adp-disable;
131	power-active-high;
132	over-current-active-low;
133	usb-role-switch;
134	status = "okay";
135
136	port {
137		usb1_drd_sw: endpoint {
138			remote-endpoint = <&usb_dr_connector>;
139		};
140	};
141};
142
143&usbotg2 {
144	dr_mode = "host";
145	disable-over-current;
146	vbus-supply = <&reg_hub_vbus>;
147	status = "okay";
148};
149
150&iomuxc {
151	pinctrl_ecspi1: ecspi1grp {
152		fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x00000006>,
153			   <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x00000006>,
154			   <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x00000006>,
155			   <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x00000006>;
156	};
157
158	pinctrl_ecspi2: ecspi2grp {
159		fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x00000006>,
160			   <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x00000006>,
161			   <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x00000006>,
162			   <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x00000006>;
163	};
164
165	pinctrl_expander: expandergrp {
166		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x94>;
167	};
168
169	pinctrl_fec1: fec1grp {
170		fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002>,
171			   <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002>,
172			   <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x14>,
173			   <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x14>,
174			   <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x14>,
175			   <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x14>,
176			   <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x90>,
177			   <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x90>,
178			   <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x90>,
179			   <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x90>,
180			   <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x14>,
181			   <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x90>,
182			   <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90>,
183			   <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14>;
184	};
185
186	pinctrl_gpiobutton: gpiobuttongrp {
187		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x84>,
188			   <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x84>,
189			   <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x84>;
190	};
191
192	pinctrl_gpioled: gpioledgrp {
193		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x84>,
194			   <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14		0x84>;
195	};
196
197	pinctrl_i2c2: i2c2grp {
198		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000004>,
199			   <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000004>;
200	};
201
202	pinctrl_i2c2_gpio: i2c2gpiogrp {
203		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000004>,
204			   <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000004>;
205	};
206
207	pinctrl_i2c3: i2c3grp {
208		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000004>,
209			   <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000004>;
210	};
211
212	pinctrl_i2c3_gpio: i2c3gpiogrp {
213		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000004>,
214			   <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000004>;
215	};
216
217	pinctrl_pwm3: pwm3grp {
218		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT		0x14>;
219	};
220
221	pinctrl_pwm4: pwm4grp {
222		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT		0x14>;
223	};
224
225	pinctrl_sai3: sai3grp {
226		fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0x94>,
227			   <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0x94>,
228			   <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0x94>,
229			   <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0x94>,
230			   <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0x94>,
231			   <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0x94>,
232			   <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0x94>;
233	};
234
235	pinctrl_uart1: uart1grp {
236		fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x16>,
237			   <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x16>;
238	};
239
240	pinctrl_uart2: uart2grp {
241		fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x16>,
242			   <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x16>;
243	};
244
245	pinctrl_uart3: uart3grp {
246		fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x16>,
247			   <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x16>;
248	};
249
250	pinctrl_uart4: uart4grp {
251		fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x16>,
252			   <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x16>;
253	};
254
255	pinctrl_usbotg1: usbotg1grp {
256		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x84>,
257			   <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x84>;
258	};
259
260	pinctrl_usb1_connector: usb1-connectorgrp {
261		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c0>;
262	};
263
264	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
265		fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x84>;
266	};
267
268	pinctrl_usdhc2: usdhc2grp {
269		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
270			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
271			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
272			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
273			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
274			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
275			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
276	};
277
278	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
279		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
280			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
281			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
282			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
283			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
284			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
285			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
286	};
287
288	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
289		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
290			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
291			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
292			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
293			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
294			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
295			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
296	};
297};
298