1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 Protonic Holland 4 * Copyright 2019 NXP 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/usb/pd.h> 10#include "imx8mm.dtsi" 11 12/ { 13 model = "Protonic PRT8MM"; 14 compatible = "prt,prt8mm", "fsl,imx8mm"; 15 16 chosen { 17 stdout-path = &uart4; 18 }; 19 20 memory@40000000 { 21 device_type = "memory"; 22 reg = <0x0 0x40000000 0 0x40000000>; 23 }; 24 25 leds { 26 compatible = "gpio-leds"; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_gpio_leds>; 29 30 debug-led0 { 31 label = "DEBUG_LED0"; 32 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; 33 linux,default-trigger = "heartbeat"; 34 }; 35 36 debug-led1 { 37 label = "DEBUG_LED1"; 38 gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; 39 linux,default-trigger = "cpu"; 40 }; 41 }; 42 43 sound-ssm2518 { 44 compatible = "simple-audio-card"; 45 simple-audio-card,name = "ssm2518-audio"; 46 simple-audio-card,format = "i2s"; 47 simple-audio-card,frame-master = <&cpudai>; 48 simple-audio-card,bitclock-master = <&cpudai>; 49 50 cpudai: simple-audio-card,cpu { 51 sound-dai = <&sai3>; 52 }; 53 54 simple-audio-card,codec { 55 sound-dai = <&ssm2518>; 56 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 57 }; 58 }; 59}; 60 61&i2c1 { 62 clock-frequency = <400000>; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_i2c1>; 65 status = "okay"; 66 67 ssm2518: audio-codec@34 { 68 compatible = "adi,ssm2518"; 69 reg = <0x34>; 70 #sound-dai-cells = <0>; 71 }; 72}; 73 74&i2c2 { 75 clock-frequency = <400000>; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_i2c2>; 78 status = "okay"; 79 80 regulator@60 { 81 compatible = "fcs,fan53555"; 82 reg = <0x60>; 83 regulator-name = "0V9_CORE"; 84 regulator-min-microvolt = <900000>; 85 regulator-max-microvolt = <980000>; 86 regulator-boot-on; 87 regulator-always-on; 88 }; 89}; 90 91&i2c3 { 92 clock-frequency = <400000>; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_i2c3>; 95 status = "okay"; 96 97 rtc@51 { 98 compatible = "nxp,pcf85363"; 99 reg = <0x51>; 100 }; 101 102 touchscreeen@5d { 103 compatible = "goodix,gt911"; 104 reg = <0x5d>; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_touchscreen>; 107 interrupt-parent = <&gpio1>; 108 interrupts = <8 IRQ_TYPE_NONE>; 109 irq-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; 110 reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; 111 }; 112 113 temp-sense@70 { 114 compatible = "ti,tmp103"; 115 reg = <0x70>; 116 }; 117}; 118 119&sai3 { 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_sai3>; 122 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 123 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 124 assigned-clock-rates = <12288000>; 125 fsl,sai-mclk-direction-output; 126 fsl,sai-asynchronous; 127 status = "okay"; 128}; 129 130&snvs_pwrkey { 131 status = "okay"; 132}; 133 134&uart4 { 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_uart4>; 137 status = "okay"; 138}; 139 140&usbotg1 { 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_usbotg1>; 143 dr_mode = "host"; 144 disable-over-current; 145 power-active-high; 146 status = "okay"; 147}; 148 149&usdhc2 { 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_usdhc2>; 152 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 153 assigned-clock-rates = <100000000>; 154 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 155 bus-width = <4>; 156 status = "okay"; 157}; 158 159&usdhc3 { 160 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 161 pinctrl-0 = <&pinctrl_usdhc3>; 162 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 163 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 164 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 165 assigned-clock-rates = <400000000>; 166 bus-width = <8>; 167 non-removable; 168 no-sdio; 169 no-sd; 170 status = "okay"; 171}; 172 173&wdog1 { 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_wdog>; 176 fsl,ext-reset-output; 177 status = "okay"; 178}; 179 180&iomuxc { 181 pinctrl_gpio_leds: ledsgrp { 182 fsl,pins = < 183 MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x00 184 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x00 185 >; 186 }; 187 188 pinctrl_i2c1: i2c1grp { 189 fsl,pins = < 190 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c3 191 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c3 192 >; 193 }; 194 195 pinctrl_i2c2: i2c2grp { 196 fsl,pins = < 197 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3 198 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3 199 >; 200 }; 201 202 pinctrl_i2c3: i2c3grp { 203 fsl,pins = < 204 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c3 205 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c3 206 >; 207 }; 208 209 pinctrl_sai3: sai3grp { 210 fsl,pins = < 211 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 212 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 213 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 214 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 215 >; 216 }; 217 218 pinctrl_touchscreen: tsgrp { 219 fsl,pins = < 220 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x80 221 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 222 >; 223 }; 224 225 pinctrl_uart4: uart4grp { 226 fsl,pins = < 227 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040 228 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040 229 >; 230 }; 231 232 pinctrl_usbotg1: usbotg1grp { 233 fsl,pins = < 234 MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x000 235 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x000 236 >; 237 }; 238 239 pinctrl_usdhc2: usdhc2grp { 240 fsl,pins = < 241 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 242 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 243 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 244 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 245 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 246 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 247 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0d4 248 >; 249 }; 250 251 pinctrl_usdhc3: usdhc3grp { 252 fsl,pins = < 253 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 254 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 255 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 256 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 257 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 258 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 259 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 260 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 261 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 262 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 263 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 264 >; 265 }; 266 267 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 268 fsl,pins = < 269 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 270 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 271 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 272 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 273 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 274 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 275 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 276 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 277 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 278 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 279 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 280 >; 281 }; 282 283 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 284 fsl,pins = < 285 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 286 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 287 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 288 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 289 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 290 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 291 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 292 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 293 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 294 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 295 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 296 >; 297 }; 298 299 pinctrl_wdog: wdoggrp { 300 fsl,pins = < 301 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 302 >; 303 }; 304}; 305