1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2021 PHYTEC Messtechnik GmbH 4 * Author: Jens Lang <j.lang@phytec.de> 5 * 6 * Tauri-L RS232 + RS485: 7 * - GPIO3_20 uart4_rs485_en needs to be driven high (active) 8 * - GPIO3_25 RS485_DE Driver enable 9 */ 10 11#include <dt-bindings/clock/imx8mm-clock.h> 12#include <dt-bindings/gpio/gpio.h> 13#include "imx8mm-pinfunc.h" 14 15/dts-v1/; 16/plugin/; 17 18&{/} { 19 compatible = "phytec,imx8mm-phygate-tauri-l"; 20 21}; 22 23&gpio3 { 24 pinctrl-names = "default"; 25 pinctrl-0 = <&pinctrl_gpio3_hog>; 26 27 uart4_rs485_en { 28 gpio-hog; 29 gpios = <20 GPIO_ACTIVE_HIGH>; 30 output-high; 31 line-name = "uart4_rs485_en"; 32 }; 33}; 34 35/* UART2 - RS232 */ 36&uart2 { 37 pinctrl-names = "default"; 38 pinctrl-0 = <&pinctrl_uart2>; 39 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 40 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 41 status = "okay"; 42}; 43 44/* UART4 - RS485 */ 45&uart4 { 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_uart4>; 48 assigned-clocks = <&clk IMX8MM_CLK_UART4>; 49 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 50 rts-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; 51 linux,rs485-enabled-at-boot-time; 52 status = "okay"; 53}; 54 55&iomuxc { 56 pinctrl_gpio3_hog: gpio3hoggrp { 57 fsl,pins = < 58 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49 59 >; 60 }; 61 62 pinctrl_uart2: uart2grp { 63 fsl,pins = < 64 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 65 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 66 >; 67 }; 68 69 pinctrl_uart4: uart4grp { 70 fsl,pins = < 71 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 72 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 73 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x49 74 >; 75 }; 76}; 77