1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2021 PHYTEC Messtechnik GmbH 4 * Author: Jens Lang <j.lang@phytec.de> 5 * 6 * Tauri-L 2 x RS232: 7 * - GPIO3_20 uart4_rs485_en needs to be driven low (inactive) 8 */ 9 10#include <dt-bindings/clock/imx8mm-clock.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "imx8mm-pinfunc.h" 13 14/dts-v1/; 15/plugin/; 16 17&{/} { 18 compatible = "phytec,imx8mm-phygate-tauri-l"; 19 20}; 21 22&gpio3 { 23 pinctrl-names = "default"; 24 pinctrl-0 = <&pinctrl_gpio3_hog>; 25 26 uart4_rs485_en { 27 gpio-hog; 28 gpios = <20 GPIO_ACTIVE_HIGH>; 29 output-low; 30 line-name = "uart4_rs485_en"; 31 }; 32}; 33 34/* UART2 - RS232 */ 35&uart2 { 36 pinctrl-names = "default"; 37 pinctrl-0 = <&pinctrl_uart2>; 38 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 39 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 40 status = "okay"; 41}; 42 43/* UART4 - RS232 */ 44&uart4 { 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_uart4>; 47 assigned-clocks = <&clk IMX8MM_CLK_UART4>; 48 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 49 status = "okay"; 50}; 51 52&iomuxc { 53 pinctrl_gpio3_hog: gpio3hoggrp { 54 fsl,pins = < 55 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49 56 >; 57 }; 58 59 pinctrl_uart2: uart2grp { 60 fsl,pins = < 61 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 62 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 63 >; 64 }; 65 66 pinctrl_uart4: uart4grp { 67 fsl,pins = < 68 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 69 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 70 >; 71 }; 72}; 73