1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH 4 * Author: Teresa Remmet <t.remmet@phytec.de> 5 */ 6 7#include "imx8mm.dtsi" 8#include <dt-bindings/net/ti-dp83867.h> 9 10/ { 11 model = "PHYTEC phyCORE-i.MX8MM"; 12 compatible = "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 13 14 aliases { 15 rtc0 = &rv3028; 16 rtc1 = &snvs_rtc; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x0 0x40000000 0 0x80000000>; 22 }; 23 24 reg_vdd_3v3_s: regulator-vdd-3v3-s { 25 compatible = "regulator-fixed"; 26 regulator-always-on; 27 regulator-boot-on; 28 regulator-max-microvolt = <3300000>; 29 regulator-min-microvolt = <3300000>; 30 regulator-name = "VDD_3V3_S"; 31 }; 32}; 33 34&A53_0 { 35 cpu-supply = <®_vdd_arm>; 36}; 37 38&A53_1 { 39 cpu-supply = <®_vdd_arm>; 40}; 41 42&A53_2 { 43 cpu-supply = <®_vdd_arm>; 44}; 45 46&A53_3 { 47 cpu-supply = <®_vdd_arm>; 48}; 49 50&ddrc { 51 operating-points-v2 = <&ddrc_opp_table>; 52 53 ddrc_opp_table: opp-table { 54 compatible = "operating-points-v2"; 55 56 opp-25000000 { 57 opp-hz = /bits/ 64 <25000000>; 58 }; 59 60 opp-100000000 { 61 opp-hz = /bits/ 64 <100000000>; 62 }; 63 64 opp-750000000 { 65 opp-hz = /bits/ 64 <750000000>; 66 }; 67 }; 68}; 69 70/* Ethernet */ 71&fec1 { 72 fsl,magic-packet; 73 phy-mode = "rgmii-id"; 74 phy-handle = <ðphy0>; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_fec1>; 77 status = "okay"; 78 79 mdio { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 ethphy0: ethernet-phy@0 { 84 compatible = "ethernet-phy-ieee802.3-c22"; 85 enet-phy-lane-no-swap; 86 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 87 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 88 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 89 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 90 reg = <0>; 91 reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 92 reset-assert-us = <1000>; 93 reset-deassert-us = <1000>; 94 }; 95 }; 96}; 97 98/* SPI Flash */ 99&flexspi { 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_flexspi0>; 102 status = "okay"; 103 104 som_flash: flash@0 { 105 #address-cells = <1>; 106 #size-cells = <1>; 107 compatible = "jedec,spi-nor"; 108 reg = <0>; 109 spi-max-frequency = <80000000>; 110 spi-rx-bus-width = <4>; 111 spi-tx-bus-width = <1>; 112 }; 113}; 114 115&gpio1 { 116 gpio-line-names = "", "", "WDOG_INT", "X_RTC_INT", 117 "", "", "", "RESET_ETHPHY", 118 "", "", "nENABLE_FLATLINK"; 119}; 120 121/* I2C1 */ 122&i2c1 { 123 clock-frequency = <400000>; 124 pinctrl-names = "default","gpio"; 125 pinctrl-0 = <&pinctrl_i2c1>; 126 pinctrl-1 = <&pinctrl_i2c1_gpio>; 127 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 128 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 129 status = "okay"; 130 131 pmic@8 { 132 compatible = "nxp,pf8121a"; 133 reg = <0x08>; 134 135 regulators { 136 reg_nvcc_sd1: ldo1 { 137 regulator-always-on; 138 regulator-boot-on; 139 regulator-max-microvolt = <3300000>; 140 regulator-min-microvolt = <3300000>; 141 regulator-name = "NVCC_SD1 (LDO1)"; 142 143 regulator-state-mem { 144 regulator-off-in-suspend; 145 }; 146 }; 147 148 reg_nvcc_sd2: ldo2 { 149 regulator-always-on; 150 regulator-boot-on; 151 regulator-max-microvolt = <3300000>; 152 regulator-min-microvolt = <1800000>; 153 regulator-name = "NVCC_SD2 (LDO2)"; 154 155 regulator-state-mem { 156 regulator-off-in-suspend; 157 }; 158 }; 159 160 reg_vcc_enet: ldo3 { 161 regulator-always-on; 162 regulator-boot-on; 163 regulator-max-microvolt = <2500000>; 164 regulator-min-microvolt = <1500000>; 165 regulator-name = "VCC_ENET_2V5 (LDO3)"; 166 167 regulator-state-mem { 168 regulator-off-in-suspend; 169 }; 170 }; 171 172 reg_vdda_1v8: ldo4 { 173 regulator-always-on; 174 regulator-boot-on; 175 regulator-max-microvolt = <1800000>; 176 regulator-min-microvolt = <1500000>; 177 regulator-name = "VDDA_1V8 (LDO4)"; 178 179 regulator-state-mem { 180 regulator-on-in-suspend; 181 regulator-suspend-min-microvolt = <1500000>; 182 regulator-suspend-max-microvolt = <1500000>; 183 }; 184 }; 185 186 reg_soc_vdda_phy: buck1 { 187 regulator-always-on; 188 regulator-boot-on; 189 regulator-max-microvolt = <900000>; 190 regulator-min-microvolt = <400000>; 191 regulator-name = "VDD_SOC_VDDA_PHY_0P8 (BUCK1)"; 192 193 regulator-state-mem { 194 regulator-on-in-suspend; 195 regulator-suspend-min-microvolt = <400000>; 196 regulator-suspend-max-microvolt = <400000>; 197 }; 198 }; 199 200 reg_vdd_gpu_dram: buck2 { 201 regulator-always-on; 202 regulator-boot-on; 203 regulator-max-microvolt = <1000000>; 204 regulator-min-microvolt = <1000000>; 205 regulator-name = "VDD_GPU_DRAM (BUCK2)"; 206 207 regulator-state-mem { 208 regulator-on-in-suspend; 209 regulator-suspend-max-microvolt = <1000000>; 210 regulator-suspend-min-microvolt = <1000000>; 211 }; 212 }; 213 214 reg_vdd_vpu: buck3 { 215 regulator-always-on; 216 regulator-boot-on; 217 regulator-max-microvolt = <1000000>; 218 regulator-min-microvolt = <400000>; 219 regulator-name = "VDD_VPU (BUCK3)"; 220 221 regulator-state-mem { 222 regulator-off-in-suspend; 223 }; 224 }; 225 226 reg_vdd_mipi: buck4 { 227 regulator-always-on; 228 regulator-boot-on; 229 regulator-max-microvolt = <1050000>; 230 regulator-min-microvolt = <900000>; 231 regulator-name = "VDD_MIPI_0P9 (BUCK4)"; 232 233 regulator-state-mem { 234 regulator-off-in-suspend; 235 }; 236 }; 237 238 reg_vdd_arm: buck5 { 239 regulator-always-on; 240 regulator-boot-on; 241 regulator-max-microvolt = <1050000>; 242 regulator-min-microvolt = <400000>; 243 regulator-name = "VDD_ARM (BUCK5)"; 244 245 regulator-state-mem { 246 regulator-off-in-suspend; 247 }; 248 }; 249 250 reg_vdd_1v8: buck6 { 251 regulator-always-on; 252 regulator-boot-on; 253 regulator-max-microvolt = <1800000>; 254 regulator-min-microvolt = <1800000>; 255 regulator-name = "VDD_1V8 (BUCK6)"; 256 257 regulator-state-mem { 258 regulator-on-in-suspend; 259 regulator-suspend-max-microvolt = <1800000>; 260 regulator-suspend-min-microvolt = <1800000>; 261 }; 262 }; 263 264 reg_nvcc_dram: buck7 { 265 regulator-always-on; 266 regulator-boot-on; 267 regulator-max-microvolt = <1100000>; 268 regulator-min-microvolt = <1100000>; 269 regulator-name = "NVCC_DRAM_1P1V (BUCK7)"; 270 }; 271 272 reg_vsnvs: vsnvs { 273 regulator-always-on; 274 regulator-boot-on; 275 regulator-max-microvolt = <1800000>; 276 regulator-min-microvolt = <1800000>; 277 regulator-name = "NVCC_SNVS_1P8 (VSNVS)"; 278 }; 279 }; 280 }; 281 282 sn65dsi83: bridge@2d { 283 compatible = "ti,sn65dsi83"; 284 enable-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_sn65dsi83>; 287 reg = <0x2d>; 288 status = "disabled"; 289 }; 290 291 eeprom@51 { 292 compatible = "atmel,24c32"; 293 pagesize = <32>; 294 reg = <0x51>; 295 vcc-supply = <®_vdd_3v3_s>; 296 }; 297 298 rv3028: rtc@52 { 299 compatible = "microcrystal,rv3028"; 300 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 301 interrupt-parent = <&gpio1>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_rtc>; 304 reg = <0x52>; 305 }; 306}; 307 308/* EMMC */ 309&usdhc3 { 310 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; 311 assigned-clock-rates = <400000000>; 312 bus-width = <8>; 313 keep-power-in-suspend; 314 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 315 pinctrl-0 = <&pinctrl_usdhc3>; 316 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 317 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 318 non-removable; 319 status = "okay"; 320}; 321 322/* Watchdog */ 323&wdog1 { 324 fsl,ext-reset-output; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_wdog>; 327 status = "okay"; 328}; 329 330&iomuxc { 331 pinctrl_fec1: fec1grp { 332 fsl,pins = < 333 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x2 334 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x2 335 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x90 336 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x90 337 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x90 338 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x90 339 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x90 340 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90 341 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x16 342 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x16 343 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x16 344 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x16 345 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x16 346 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x16 347 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x10 348 >; 349 }; 350 351 pinctrl_flexspi0: flexspi0grp { 352 fsl,pins = < 353 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 354 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 355 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 356 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 357 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 358 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 359 >; 360 }; 361 362 pinctrl_i2c1: i2c1grp { 363 fsl,pins = < 364 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c0 365 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c0 366 >; 367 }; 368 369 pinctrl_i2c1_gpio: i2c1gpiogrp { 370 fsl,pins = < 371 MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1e0 372 MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1e0 373 >; 374 }; 375 376 pinctrl_rtc: rtcgrp { 377 fsl,pins = < 378 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 379 >; 380 }; 381 382 pinctrl_sn65dsi83: sn65dsi83grp { 383 fsl,pins = < 384 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 385 >; 386 }; 387 388 pinctrl_usdhc3: usdhc3grp { 389 fsl,pins = < 390 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 391 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 392 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 393 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 394 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 395 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 396 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 397 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 398 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 399 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 400 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 401 >; 402 }; 403 404 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 405 fsl,pins = < 406 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 407 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 408 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 409 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 410 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 411 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 412 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 413 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 414 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 415 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 416 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 417 >; 418 }; 419 420 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 421 fsl,pins = < 422 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 423 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 424 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 425 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 426 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 427 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 428 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 429 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 430 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 431 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 432 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 433 >; 434 }; 435 436 pinctrl_wdog: wdoggrp { 437 fsl,pins = < 438 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x26 439 >; 440 }; 441}; 442