1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH 4 * Author: Teresa Remmet <t.remmet@phytec.de> 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/phy/phy-imx8-pcie.h> 12#include "imx8mm-phycore-som.dtsi" 13 14/ { 15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; 16 compatible = "phytec,imx8mm-phyboard-polis-rdk", 17 "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 18 19 chosen { 20 stdout-path = &uart3; 21 }; 22 23 bt_osc_32k: bt-lp-clock { 24 compatible = "fixed-clock"; 25 clock-frequency = <32768>; 26 clock-output-names = "bt_osc_32k"; 27 #clock-cells = <0>; 28 }; 29 30 can_osc_40m: can-clock { 31 compatible = "fixed-clock"; 32 clock-frequency = <40000000>; 33 clock-output-names = "can_osc_40m"; 34 #clock-cells = <0>; 35 }; 36 37 fan { 38 compatible = "gpio-fan"; 39 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; 40 gpio-fan,speed-map = <0 0 41 13000 1>; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_fan>; 44 #cooling-cells = <2>; 45 }; 46 47 leds { 48 compatible = "gpio-leds"; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_leds>; 51 52 led-0 { 53 color = <LED_COLOR_ID_RED>; 54 function = LED_FUNCTION_DISK; 55 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 56 linux,default-trigger = "mmc2"; 57 }; 58 59 led-1 { 60 color = <LED_COLOR_ID_BLUE>; 61 function = LED_FUNCTION_DISK; 62 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; 63 linux,default-trigger = "mmc1"; 64 }; 65 66 led-2 { 67 color = <LED_COLOR_ID_GREEN>; 68 function = LED_FUNCTION_CPU; 69 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 70 linux,default-trigger = "heartbeat"; 71 }; 72 }; 73 74 usdhc1_pwrseq: pwr-seq { 75 compatible = "mmc-pwrseq-simple"; 76 post-power-on-delay-ms = <100>; 77 power-off-delay-us = <60>; 78 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 79 }; 80 81 reg_can_en: regulator-can-en { 82 compatible = "regulator-fixed"; 83 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_can_en>; 86 regulator-max-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>; 88 regulator-name = "CAN_EN"; 89 startup-delay-us = <20>; 90 }; 91 92 reg_usb_otg1_vbus: regulator-usb-otg1 { 93 compatible = "regulator-fixed"; 94 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 95 enable-active-high; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; 98 regulator-name = "usb_otg1_vbus"; 99 regulator-max-microvolt = <5000000>; 100 regulator-min-microvolt = <5000000>; 101 }; 102 103 reg_usdhc2_vmmc: regulator-usdhc2 { 104 compatible = "regulator-fixed"; 105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 106 enable-active-high; 107 off-on-delay-us = <20000>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 110 regulator-max-microvolt = <3300000>; 111 regulator-min-microvolt = <3300000>; 112 regulator-name = "VSD_3V3"; 113 }; 114 115 reg_vcc_3v3: regulator-vcc-3v3 { 116 compatible = "regulator-fixed"; 117 regulator-max-microvolt = <3300000>; 118 regulator-min-microvolt = <3300000>; 119 regulator-name = "VCC_3V3"; 120 }; 121}; 122 123/* SPI - CAN MCP251XFD */ 124&ecspi1 { 125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_ecspi1>; 128 status = "okay"; 129 130 can0: can@0 { 131 compatible = "microchip,mcp251xfd"; 132 clocks = <&can_osc_40m>; 133 interrupt-parent = <&gpio1>; 134 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_can_int>; 137 reg = <0>; 138 spi-max-frequency = <20000000>; 139 xceiver-supply = <®_can_en>; 140 }; 141}; 142 143/* TPM */ 144&ecspi2 { 145 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_ecspi2>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 status = "okay"; 151 152 tpm: tpm@0 { 153 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 154 interrupt-parent = <&gpio2>; 155 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_tpm>; 158 reg = <0>; 159 spi-max-frequency = <43000000>; 160 }; 161}; 162 163&gpio1 { 164 gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT", 165 "", "", "", "RESET_ETHPHY", 166 "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", 167 "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; 168}; 169 170&gpio2 { 171 gpio-line-names = "", "", "", "", 172 "", "", "BT_REG_ON", "WL_REG_ON", 173 "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", 174 "X_SD2_CD_B", "", "", "", 175 "", "", "", "SD2_RESET_B"; 176}; 177 178&gpio4 { 179 gpio-line-names = "", "", "", "", 180 "", "", "", "", 181 "FAN", "miniPCIe_nPERST", "", "", 182 "COEX1", "COEX2"; 183}; 184 185&gpio5 { 186 gpio-line-names = "", "", "", "", 187 "", "", "", "", 188 "", "ECSPI1_SS0"; 189}; 190 191&i2c4 { 192 clock-frequency = <400000>; 193 pinctrl-names = "default", "gpio"; 194 pinctrl-0 = <&pinctrl_i2c4>; 195 pinctrl-1 = <&pinctrl_i2c4_gpio>; 196 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 197 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 198}; 199 200/* PCIe */ 201&pcie0 { 202 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 203 <&clk IMX8MM_CLK_PCIE1_CTRL>; 204 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 205 <&clk IMX8MM_SYS_PLL2_250M>; 206 assigned-clock-rates = <10000000>, <250000000>; 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_pcie>; 209 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; 210 status = "okay"; 211}; 212 213&pcie_phy { 214 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 215 fsl,clkreq-unsupported; 216 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 217 fsl,tx-deemph-gen1 = <0x2d>; 218 fsl,tx-deemph-gen2 = <0xf>; 219 status = "okay"; 220}; 221 222/* RTC */ 223&rv3028 { 224 interrupt-parent = <&gpio1>; 225 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 226 pinctrl-0 = <&pinctrl_rtc>; 227 pinctrl-names = "default"; 228 aux-voltage-chargeable = <1>; 229 trickle-resistor-ohms = <3000>; 230 wakeup-source; 231}; 232 233&snvs_pwrkey { 234 status = "okay"; 235}; 236 237/* UART - RS232/RS485 */ 238&uart1 { 239 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 240 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_uart1>; 243 uart-has-rtscts; 244 status = "okay"; 245}; 246 247/* UART - Sterling-LWB Bluetooth */ 248&uart2 { 249 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 250 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 251 fsl,dte-mode; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_uart2_bt>; 254 uart-has-rtscts; 255 status = "okay"; 256 257 bluetooth { 258 compatible = "brcm,bcm43438-bt"; 259 clocks = <&bt_osc_32k>; 260 clock-names = "lpo"; 261 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 262 interrupt-names = "host-wakeup"; 263 interrupt-parent = <&gpio2>; 264 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 265 max-speed = <2000000>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&pinctrl_bt>; 268 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 269 vbat-supply = <®_vcc_3v3>; 270 vddio-supply = <®_vcc_3v3>; 271 }; 272}; 273 274/* UART - console */ 275&uart3 { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_uart3>; 278 status = "okay"; 279}; 280 281/* USB */ 282&usbotg1 { 283 adp-disable; 284 dr_mode = "otg"; 285 over-current-active-low; 286 samsung,picophy-pre-emp-curr-control = <3>; 287 samsung,picophy-dc-vol-level-adjust = <7>; 288 srp-disable; 289 vbus-supply = <®_usb_otg1_vbus>; 290 status = "okay"; 291}; 292 293&usbotg2 { 294 disable-over-current; 295 dr_mode = "host"; 296 samsung,picophy-pre-emp-curr-control = <3>; 297 samsung,picophy-dc-vol-level-adjust = <7>; 298 status = "okay"; 299}; 300 301/* SDIO - Sterling-LWB Wifi */ 302&usdhc1 { 303 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; 304 assigned-clock-rates = <200000000>; 305 bus-width = <4>; 306 mmc-pwrseq = <&usdhc1_pwrseq>; 307 non-removable; 308 no-1-8-v; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 status = "okay"; 314 315 brcmf: wifi@1 { 316 compatible = "brcm,bcm4329-fmac"; 317 reg = <1>; 318 }; 319}; 320 321/* SD-Card */ 322&usdhc2 { 323 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 324 assigned-clock-rates = <200000000>; 325 bus-width = <4>; 326 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 327 disable-wp; 328 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 329 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 330 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 331 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 332 vmmc-supply = <®_usdhc2_vmmc>; 333 vqmmc-supply = <®_nvcc_sd2>; 334 status = "okay"; 335}; 336 337&iomuxc { 338 pinctrl_bt: btgrp { 339 fsl,pins = < 340 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 341 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 342 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x140 343 >; 344 }; 345 346 pinctrl_can_en: can-engrp { 347 fsl,pins = < 348 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 349 >; 350 }; 351 352 pinctrl_can_int: can-intgrp { 353 fsl,pins = < 354 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 355 >; 356 }; 357 358 pinctrl_ecspi1: ecspi1grp { 359 fsl,pins = < 360 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 361 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 362 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 363 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 364 >; 365 }; 366 367 pinctrl_ecspi2: ecspi2grp { 368 fsl,pins = < 369 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x80 370 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x80 371 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x80 372 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 373 >; 374 }; 375 376 pinctrl_fan: fan0grp { 377 fsl,pins = < 378 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 379 >; 380 }; 381 382 pinctrl_i2c4: i2c4grp { 383 fsl,pins = < 384 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 385 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 386 >; 387 }; 388 389 pinctrl_i2c4_gpio: i2c4gpiogrp { 390 fsl,pins = < 391 MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e2 392 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e2 393 >; 394 }; 395 396 pinctrl_leds: leds1grp { 397 fsl,pins = < 398 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 399 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 400 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 401 >; 402 }; 403 404 pinctrl_pcie: pciegrp { 405 fsl,pins = < 406 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 407 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 408 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 409 >; 410 }; 411 412 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 413 fsl,pins = < 414 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 415 >; 416 }; 417 418 pinctrl_rtc: rtcgrp { 419 fsl,pins = < 420 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 421 >; 422 }; 423 424 pinctrl_tpm: tpmgrp { 425 fsl,pins = < 426 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 427 >; 428 }; 429 430 pinctrl_uart1: uart1grp { 431 fsl,pins = < 432 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 433 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 434 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 435 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 436 >; 437 }; 438 439 pinctrl_uart2_bt: uart2btgrp { 440 fsl,pins = < 441 MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 442 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 443 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 444 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 445 >; 446 }; 447 448 pinctrl_uart3: uart3grp { 449 fsl,pins = < 450 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 451 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 452 >; 453 }; 454 455 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { 456 fsl,pins = < 457 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 458 >; 459 }; 460 461 pinctrl_usdhc1: usdhc1grp { 462 fsl,pins = < 463 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 464 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 465 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 466 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 467 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 468 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 469 >; 470 }; 471 472 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 473 fsl,pins = < 474 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 475 >; 476 }; 477 478 pinctrl_usdhc2: usdhc2grp { 479 fsl,pins = < 480 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 481 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 482 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 483 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 484 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 485 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 486 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 487 >; 488 }; 489 490 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 491 fsl,pins = < 492 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 493 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 494 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 495 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 496 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 497 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 498 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 499 >; 500 }; 501 502 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 503 fsl,pins = < 504 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 505 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 506 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 507 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 508 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 509 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 510 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 511 >; 512 }; 513 514 pinctrl_wlan: wlangrp { 515 fsl,pins = < 516 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 517 >; 518 }; 519}; 520