xref: /linux/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts (revision db4a3f0fbedb0398f77b9047e8b8bb2b49f355bb) 
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2022 Kontron Electronics GmbH
4 */
5
6/dts-v1/;
7
8#include "imx8mm-kontron-osm-s.dtsi"
9
10/ {
11	model = "Kontron BL i.MX8MM OSM-S (N802X S)";
12	compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm";
13
14	aliases {
15		ethernet1 = &usbnet;
16	};
17
18	/* fixed crystal dedicated to mcp2542fd */
19	osc_can: clock-osc-can {
20		compatible = "fixed-clock";
21		#clock-cells = <0>;
22		clock-frequency = <40000000>;
23		clock-output-names = "osc-can";
24	};
25
26	leds {
27		compatible = "gpio-leds";
28
29		led1 {
30			label = "led1";
31			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
32			linux,default-trigger = "heartbeat";
33		};
34
35		led2 {
36			label = "led2";
37			gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
38		};
39
40		led3 {
41			label = "led3";
42			gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
43		};
44	};
45
46	pwm-beeper {
47		compatible = "pwm-beeper";
48		pwms = <&pwm2 0 5000 0>;
49	};
50
51	reg_vdd_5v: regulator-5v {
52		compatible = "regulator-fixed";
53		regulator-always-on;
54		regulator-min-microvolt = <5000000>;
55		regulator-max-microvolt = <5000000>;
56		regulator-name = "vdd-5v";
57	};
58};
59
60&ecspi2 {
61	status = "okay";
62
63	can@0 {
64		compatible = "microchip,mcp251xfd";
65		reg = <0>;
66		pinctrl-names = "default";
67		pinctrl-0 = <&pinctrl_can>;
68		clocks = <&osc_can>;
69		interrupts-extended = <&gpio5 1 IRQ_TYPE_LEVEL_LOW>;
70		/*
71		 * Limit the SPI clock to 15 MHz to prevent issues
72		 * with corrupted data due to chip errata.
73		 */
74		spi-max-frequency = <15000000>;
75		vdd-supply = <&reg_vdd_3v3>;
76		xceiver-supply = <&reg_vdd_5v>;
77	};
78};
79
80&ecspi3 {
81	status = "okay";
82
83	eeram@0 {
84		compatible = "microchip,48l640";
85		reg = <0>;
86		spi-max-frequency = <20000000>;
87	};
88};
89
90&fec1 {
91	pinctrl-names = "default";
92	pinctrl-0 = <&pinctrl_enet_rgmii>;
93	phy-connection-type = "rgmii-id";
94	phy-handle = <&ethphy>;
95	status = "okay";
96
97	mdio {
98		#address-cells = <1>;
99		#size-cells = <0>;
100
101		ethphy: ethernet-phy@0 {
102			compatible = "ethernet-phy-id4f51.e91b";
103			reg = <0>;
104			reset-assert-us = <10000>;
105			reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
106		};
107	};
108};
109
110/*
111 * Rename SoM signals according to board usage:
112 *   GPIO_B_0      -> DIO1_OUT
113 *   GPIO_B_1      -> DIO2_OUT
114 */
115&gpio1 {
116	gpio-line-names = "", "GPIO_A_0", "", "GPIO_A_1",
117			  "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",
118			  "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT",
119			  "DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#",
120			  "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3",
121			  "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1",
122			  "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)",
123			  "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)",
124			  "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0",
125			  "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2",
126			  "ETH_A_(R)(G)MII_RXD3";
127};
128
129/*
130 * Rename SoM signals according to board usage:
131 *   GPIO_B_2      -> DIO3_OUT
132 *   GPIO_B_3      -> DIO4_OUT
133 */
134&gpio3 {
135	gpio-line-names = "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5",
136			  "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1",
137			  "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1",
138			  "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4",
139			  "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT",
140			  "USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#",
141			  "PCIe_WAKE#", "USB_A_EN";
142};
143
144/*
145 * Rename SoM signals according to board usage:
146 *   GPIO_B_4      -> DIO1_IN
147 *   GPIO_B_5      -> DIO2_IN
148 *   GPIO_B_6      -> DIO3_IN
149 *   GPIO_B_7      -> DIO4_IN
150 */
151&gpio4 {
152	gpio-line-names = "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN",
153			  "DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "",
154			  "", "", "I2S_LRCLK", "I2S_BITCLK",
155			  "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN",
156			  "DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6",
157			  "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS",
158			  "UART_A_RTS", "", "", "",
159			  "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX";
160};
161
162&i2c3 {
163	status = "okay";
164
165	usb-hub@2c {
166		compatible = "microchip,usb2514b";
167		pinctrl-names = "default";
168		pinctrl-0 = <&pinctrl_usb_hub>;
169		reg = <0x2c>;
170		non-removable-ports = <0>, <3>;
171		reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
172	};
173};
174
175&pwm2 {
176	status = "okay";
177};
178
179&reg_usb2_vbus {
180	status = "disabled";
181};
182
183&reg_usdhc2_vcc {
184	status = "disabled";
185};
186
187&reg_usdhc3_vcc {
188	status = "disabled";
189};
190
191&uart1 {
192	uart-has-rtscts;
193	status = "okay";
194};
195
196&uart2 {
197	linux,rs485-enabled-at-boot-time;
198	uart-has-rtscts;
199	status = "okay";
200};
201
202&usbotg1 {
203	dr_mode = "otg";
204	status = "okay";
205};
206
207&usbotg2 {
208	dr_mode = "host";
209	disable-over-current;
210	#address-cells = <1>;
211	#size-cells = <0>;
212	status = "okay";
213
214	/* VBUS is controlled by the hub */
215	/delete-property/ vbus-supply;
216
217	usb1@1 {
218		compatible = "usb424,2514";
219		reg = <1>;
220		#address-cells = <1>;
221		#size-cells = <0>;
222
223		usbnet: ethernet@1 {
224			compatible = "usbb95,772b";
225			reg = <1>;
226			local-mac-address = [ 00 00 00 00 00 00 ];
227		};
228	};
229};
230
231&usdhc2 {
232	vmmc-supply = <&reg_vdd_3v3>;
233	status = "okay";
234};
235
236&iomuxc {
237	pinctrl_can: cangrp {
238		fsl,pins = <
239			MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1			0x19  /* SDIO_B_PWR_EN */
240		>;
241	};
242
243	pinctrl_usb_hub: usbhubgrp {
244		fsl,pins = <
245			MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2		0x19 /* SDIO_B_WP */
246		>;
247	};
248};
249