1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2018 Bang & Olufsen 4 * Copyright 2022 Pengutronix 5 */ 6 7/dts-v1/; 8 9#include "imx8mm-innocomm-wb15.dtsi" 10 11/ { 12 model = "InnoComm WB15-EVK"; 13 compatible = "innocomm,wb15-evk", "fsl,imx8mm"; 14 15 chosen { 16 stdout-path = &uart2; 17 }; 18 19 leds { 20 compatible = "gpio-leds"; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&pinctrl_gpio_leds>; 23 24 led-0 { 25 label = "debug"; 26 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 27 default-state = "off"; 28 }; 29 }; 30 31 reg_vsd_3v3: regulator-vsd-3v3 { 32 compatible = "regulator-fixed"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_reg_vsd_3v3>; 35 regulator-name = "VSD_3V3"; 36 regulator-min-microvolt = <3300000>; 37 regulator-max-microvolt = <3300000>; 38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 39 enable-active-high; 40 }; 41 42 reg_ethphy: regulator-eth-phy { 43 compatible = "regulator-fixed"; 44 pinctrl-names = "default"; 45 pinctrl-0 = <&pinctrl_fec_phy_reg>; 46 regulator-name = "PHY_3V3"; 47 regulator-min-microvolt = <3300000>; 48 regulator-max-microvolt = <3300000>; 49 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; 50 enable-active-high; 51 }; 52}; 53 54&fec1 { 55 pinctrl-names = "default"; 56 pinctrl-0 = <&pinctrl_fec>; 57 phy-mode = "rgmii-id"; 58 phy-handle = <ðphy0>; 59 fsl,magic-packet; 60 status = "okay"; 61 62 mdio { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 66 ethphy0: ethernet-phy@1 { 67 compatible = "ethernet-phy-ieee802.3-c22"; 68 reg = <0x1>; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_fec_phy>; 71 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 72 phy-supply = <®_ethphy>; 73 }; 74 }; 75}; 76 77&uart2 { 78 status = "okay"; 79}; 80 81&usbotg1 { 82 dr_mode = "otg"; 83 samsung,picophy-pre-emp-curr-control = <3>; 84 samsung,picophy-dc-vol-level-adjust = <7>; 85 disable-over-current; 86 status = "okay"; 87}; 88 89&usbotg2 { 90 dr_mode = "host"; 91 samsung,picophy-pre-emp-curr-control = <3>; 92 samsung,picophy-dc-vol-level-adjust = <7>; 93 disable-over-current; 94 status = "okay"; 95}; 96 97&usdhc2 { 98 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 99 vmmc-supply = <®_vsd_3v3>; 100 status = "okay"; 101}; 102 103&iomuxc { 104 pinctrl_fec: fec-grp { 105 fsl,pins = < 106 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 107 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 108 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 109 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 110 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 111 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 112 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 113 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 114 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 115 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 116 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 117 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 118 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 119 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 120 >; 121 }; 122 123 pinctrl_fec_phy: fec-phy-grp { 124 fsl,pins = < 125 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 126 >; 127 }; 128 129 pinctrl_fec_phy_reg: fec-phy-reg-grp { 130 fsl,pins = < 131 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x16 132 >; 133 }; 134 135 pinctrl_gpio_leds: led-grp { 136 fsl,pins = < 137 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0xd6 138 >; 139 }; 140 141 pinctrl_reg_vsd_3v3: reg-vsd-3v3-grp { 142 fsl,pins = < 143 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 144 >; 145 }; 146}; 147