1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2020 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9#include <dt-bindings/usb/pd.h> 10#include "imx8mm.dtsi" 11 12/ { 13 chosen { 14 stdout-path = &uart2; 15 }; 16 17 memory@40000000 { 18 device_type = "memory"; 19 reg = <0x0 0x40000000 0 0x80000000>; 20 }; 21 22 hdmi-connector { 23 compatible = "hdmi-connector"; 24 label = "hdmi"; 25 type = "a"; 26 27 port { 28 hdmi_connector_in: endpoint { 29 remote-endpoint = <&adv7535_out>; 30 }; 31 }; 32 }; 33 34 leds { 35 compatible = "gpio-leds"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&pinctrl_gpio_led>; 38 39 status { 40 label = "status"; 41 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 42 default-state = "on"; 43 }; 44 }; 45 46 pcie0_refclk: pcie0-refclk { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <100000000>; 50 }; 51 52 reg_pcie0: regulator-pcie { 53 compatible = "regulator-fixed"; 54 pinctrl-names = "default"; 55 pinctrl-0 = <&pinctrl_pcie0_reg>; 56 regulator-name = "MPCIE_3V3"; 57 regulator-min-microvolt = <3300000>; 58 regulator-max-microvolt = <3300000>; 59 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 60 enable-active-high; 61 }; 62 63 reg_usdhc2_vmmc: regulator-usdhc2 { 64 compatible = "regulator-fixed"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 67 regulator-name = "VSD_3V3"; 68 regulator-min-microvolt = <3300000>; 69 regulator-max-microvolt = <3300000>; 70 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 71 off-on-delay-us = <20000>; 72 enable-active-high; 73 }; 74 75 reg_1v5: regulator-1v5 { 76 compatible = "regulator-fixed"; 77 regulator-name = "VDD_1V5"; 78 regulator-min-microvolt = <1500000>; 79 regulator-max-microvolt = <1500000>; 80 }; 81 82 reg_1v8: regulator-1v8 { 83 compatible = "regulator-fixed"; 84 regulator-name = "VDD_1V8"; 85 regulator-min-microvolt = <1800000>; 86 regulator-max-microvolt = <1800000>; 87 }; 88 89 reg_vddext_3v3: regulator-vddext-3v3 { 90 compatible = "regulator-fixed"; 91 regulator-name = "VDDEXT_3V3"; 92 regulator-min-microvolt = <3300000>; 93 regulator-max-microvolt = <3300000>; 94 }; 95 96 backlight: backlight { 97 compatible = "pwm-backlight"; 98 pwms = <&pwm1 0 5000000 0>; 99 brightness-levels = <0 255>; 100 num-interpolated-steps = <255>; 101 default-brightness-level = <250>; 102 }; 103 104 ir-receiver { 105 compatible = "gpio-ir-receiver"; 106 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_ir>; 109 linux,autosuspend-period = <125>; 110 }; 111 112 audio_codec_bt_sco: audio-codec-bt-sco { 113 compatible = "linux,bt-sco"; 114 #sound-dai-cells = <1>; 115 }; 116 117 wm8524: audio-codec { 118 #sound-dai-cells = <0>; 119 compatible = "wlf,wm8524"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_gpio_wlf>; 122 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 123 }; 124 125 sound-bt-sco { 126 compatible = "simple-audio-card"; 127 simple-audio-card,name = "bt-sco-audio"; 128 simple-audio-card,format = "dsp_a"; 129 simple-audio-card,bitclock-inversion; 130 simple-audio-card,frame-master = <&btcpu>; 131 simple-audio-card,bitclock-master = <&btcpu>; 132 133 btcpu: simple-audio-card,cpu { 134 sound-dai = <&sai2>; 135 dai-tdm-slot-num = <2>; 136 dai-tdm-slot-width = <16>; 137 }; 138 139 simple-audio-card,codec { 140 sound-dai = <&audio_codec_bt_sco 1>; 141 }; 142 }; 143 144 sound-wm8524 { 145 compatible = "simple-audio-card"; 146 simple-audio-card,name = "wm8524-audio"; 147 simple-audio-card,format = "i2s"; 148 simple-audio-card,frame-master = <&cpudai>; 149 simple-audio-card,bitclock-master = <&cpudai>; 150 simple-audio-card,widgets = 151 "Line", "Left Line Out Jack", 152 "Line", "Right Line Out Jack"; 153 simple-audio-card,routing = 154 "Left Line Out Jack", "LINEVOUTL", 155 "Right Line Out Jack", "LINEVOUTR"; 156 157 cpudai: simple-audio-card,cpu { 158 sound-dai = <&sai3>; 159 dai-tdm-slot-num = <2>; 160 dai-tdm-slot-width = <32>; 161 }; 162 163 simple-audio-card,codec { 164 sound-dai = <&wm8524>; 165 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 166 }; 167 }; 168 169 sound-micfil { 170 compatible = "fsl,imx-audio-card"; 171 model = "micfil-audio"; 172 173 pri-dai-link { 174 link-name = "micfil hifi"; 175 format = "i2s"; 176 177 cpu { 178 sound-dai = <&micfil>; 179 }; 180 }; 181 }; 182 183 sound-spdif { 184 compatible = "fsl,imx-audio-spdif"; 185 model = "imx-spdif"; 186 spdif-controller = <&spdif1>; 187 spdif-out; 188 spdif-in; 189 }; 190}; 191 192&A53_0 { 193 cpu-supply = <&buck2_reg>; 194}; 195 196&A53_1 { 197 cpu-supply = <&buck2_reg>; 198}; 199 200&A53_2 { 201 cpu-supply = <&buck2_reg>; 202}; 203 204&A53_3 { 205 cpu-supply = <&buck2_reg>; 206}; 207 208&fec1 { 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_fec1>; 211 phy-mode = "rgmii-id"; 212 phy-handle = <ðphy0>; 213 fsl,magic-packet; 214 status = "okay"; 215 216 mdio { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 220 ethphy0: ethernet-phy@0 { 221 compatible = "ethernet-phy-ieee802.3-c22"; 222 reg = <0>; 223 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 224 reset-assert-us = <10000>; 225 qca,disable-smarteee; 226 vddio-supply = <&vddio>; 227 228 vddio: vddio-regulator { 229 regulator-min-microvolt = <1800000>; 230 regulator-max-microvolt = <1800000>; 231 }; 232 }; 233 }; 234}; 235 236&i2c1 { 237 clock-frequency = <400000>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_i2c1>; 240 status = "okay"; 241 242 pmic@4b { 243 compatible = "rohm,bd71847"; 244 reg = <0x4b>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_pmic>; 247 interrupt-parent = <&gpio1>; 248 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 249 rohm,reset-snvs-powered; 250 251 #clock-cells = <0>; 252 clocks = <&osc_32k>; 253 clock-output-names = "clk-32k-out"; 254 255 regulators { 256 buck1_reg: BUCK1 { 257 regulator-name = "buck1"; 258 regulator-min-microvolt = <700000>; 259 regulator-max-microvolt = <1300000>; 260 regulator-boot-on; 261 regulator-always-on; 262 regulator-ramp-delay = <1250>; 263 }; 264 265 buck2_reg: BUCK2 { 266 regulator-name = "buck2"; 267 regulator-min-microvolt = <700000>; 268 regulator-max-microvolt = <1300000>; 269 regulator-boot-on; 270 regulator-always-on; 271 regulator-ramp-delay = <1250>; 272 rohm,dvs-run-voltage = <1000000>; 273 rohm,dvs-idle-voltage = <900000>; 274 }; 275 276 buck3_reg: BUCK3 { 277 // BUCK5 in datasheet 278 regulator-name = "buck3"; 279 regulator-min-microvolt = <700000>; 280 regulator-max-microvolt = <1350000>; 281 regulator-boot-on; 282 regulator-always-on; 283 }; 284 285 buck4_reg: BUCK4 { 286 // BUCK6 in datasheet 287 regulator-name = "buck4"; 288 regulator-min-microvolt = <3000000>; 289 regulator-max-microvolt = <3300000>; 290 regulator-boot-on; 291 regulator-always-on; 292 }; 293 294 buck5_reg: BUCK5 { 295 // BUCK7 in datasheet 296 regulator-name = "buck5"; 297 regulator-min-microvolt = <1605000>; 298 regulator-max-microvolt = <1995000>; 299 regulator-boot-on; 300 regulator-always-on; 301 }; 302 303 buck6_reg: BUCK6 { 304 // BUCK8 in datasheet 305 regulator-name = "buck6"; 306 regulator-min-microvolt = <800000>; 307 regulator-max-microvolt = <1400000>; 308 regulator-boot-on; 309 regulator-always-on; 310 }; 311 312 ldo1_reg: LDO1 { 313 regulator-name = "ldo1"; 314 regulator-min-microvolt = <1600000>; 315 regulator-max-microvolt = <3300000>; 316 regulator-boot-on; 317 regulator-always-on; 318 }; 319 320 ldo2_reg: LDO2 { 321 regulator-name = "ldo2"; 322 regulator-min-microvolt = <800000>; 323 regulator-max-microvolt = <900000>; 324 regulator-boot-on; 325 regulator-always-on; 326 }; 327 328 ldo3_reg: LDO3 { 329 regulator-name = "ldo3"; 330 regulator-min-microvolt = <1800000>; 331 regulator-max-microvolt = <3300000>; 332 regulator-boot-on; 333 regulator-always-on; 334 }; 335 336 ldo4_reg: LDO4 { 337 regulator-name = "ldo4"; 338 regulator-min-microvolt = <900000>; 339 regulator-max-microvolt = <1800000>; 340 regulator-boot-on; 341 regulator-always-on; 342 }; 343 344 ldo6_reg: LDO6 { 345 regulator-name = "ldo6"; 346 regulator-min-microvolt = <900000>; 347 regulator-max-microvolt = <1800000>; 348 regulator-boot-on; 349 regulator-always-on; 350 }; 351 }; 352 }; 353}; 354 355&i2c2 { 356 clock-frequency = <400000>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_i2c2>; 359 status = "okay"; 360 361 hdmi@3d { 362 compatible = "adi,adv7535"; 363 reg = <0x3d>; 364 interrupt-parent = <&gpio1>; 365 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 366 adi,dsi-lanes = <4>; 367 avdd-supply = <&buck5_reg>; 368 dvdd-supply = <&buck5_reg>; 369 pvdd-supply = <&buck5_reg>; 370 a2vdd-supply = <&buck5_reg>; 371 v3p3-supply = <®_vddext_3v3>; 372 v1p2-supply = <&buck5_reg>; 373 374 ports { 375 #address-cells = <1>; 376 #size-cells = <0>; 377 378 port@0 { 379 reg = <0>; 380 381 adv7535_in: endpoint { 382 remote-endpoint = <&dsi_out>; 383 }; 384 }; 385 386 port@1 { 387 reg = <1>; 388 389 adv7535_out: endpoint { 390 remote-endpoint = <&hdmi_connector_in>; 391 }; 392 }; 393 394 }; 395 }; 396 397 ptn5110: tcpc@50 { 398 compatible = "nxp,ptn5110", "tcpci"; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&pinctrl_typec1>; 401 reg = <0x50>; 402 interrupt-parent = <&gpio2>; 403 interrupts = <11 8>; 404 status = "okay"; 405 406 typec1_con: connector { 407 compatible = "usb-c-connector"; 408 label = "USB-C"; 409 power-role = "dual"; 410 data-role = "dual"; 411 try-power-role = "sink"; 412 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 413 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 414 PDO_VAR(5000, 20000, 3000)>; 415 op-sink-microwatt = <15000000>; 416 self-powered; 417 418 port { 419 typec1_dr_sw: endpoint { 420 remote-endpoint = <&usb1_drd_sw>; 421 }; 422 }; 423 }; 424 }; 425}; 426 427 428&csi { 429 status = "okay"; 430}; 431 432&i2c3 { 433 clock-frequency = <400000>; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pinctrl_i2c3>; 436 status = "okay"; 437 438 pca6416: gpio@20 { 439 compatible = "nxp,pca6416"; 440 reg = <0x20>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 vcc-supply = <&buck4_reg>; 444 }; 445 446 camera@3c { 447 compatible = "ovti,ov5640"; 448 reg = <0x3c>; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_camera>; 451 clocks = <&clk IMX8MM_CLK_CLKO1>; 452 clock-names = "xclk"; 453 assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; 454 assigned-clock-parents = <&clk IMX8MM_CLK_24M>; 455 assigned-clock-rates = <24000000>; 456 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 457 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 458 DOVDD-supply = <&buck5_reg>; 459 AVDD-supply = <®_1v8>; 460 DVDD-supply = <®_1v5>; 461 462 port { 463 ov5640_to_mipi_csi2: endpoint { 464 remote-endpoint = <&imx8mm_mipi_csi_in>; 465 clock-lanes = <0>; 466 data-lanes = <1 2>; 467 }; 468 }; 469 }; 470}; 471 472&lcdif { 473 status = "okay"; 474}; 475 476&micfil { 477 #sound-dai-cells = <0>; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&pinctrl_pdm>; 480 assigned-clocks = <&clk IMX8MM_CLK_PDM>; 481 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 482 assigned-clock-rates = <196608000>; 483 status = "okay"; 484}; 485 486&mipi_csi { 487 status = "okay"; 488 489 ports { 490 port@0 { 491 imx8mm_mipi_csi_in: endpoint { 492 remote-endpoint = <&ov5640_to_mipi_csi2>; 493 data-lanes = <1 2>; 494 }; 495 }; 496 }; 497}; 498 499&mipi_dsi { 500 samsung,esc-clock-frequency = <10000000>; 501 status = "okay"; 502 503 ports { 504 port@1 { 505 reg = <1>; 506 507 dsi_out: endpoint { 508 remote-endpoint = <&adv7535_in>; 509 data-lanes = <1 2 3 4>; 510 }; 511 }; 512 }; 513}; 514 515&pcie_phy { 516 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 517 fsl,tx-deemph-gen1 = <0x2d>; 518 fsl,tx-deemph-gen2 = <0xf>; 519 clocks = <&pcie0_refclk>; 520 status = "okay"; 521}; 522 523&pcie0 { 524 pinctrl-names = "default"; 525 pinctrl-0 = <&pinctrl_pcie0>; 526 reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; 527 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, 528 <&clk IMX8MM_CLK_PCIE1_AUX>; 529 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 530 <&clk IMX8MM_CLK_PCIE1_CTRL>; 531 assigned-clock-rates = <10000000>, <250000000>; 532 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 533 <&clk IMX8MM_SYS_PLL2_250M>; 534 vpcie-supply = <®_pcie0>; 535 status = "okay"; 536}; 537 538&sai2 { 539 #sound-dai-cells = <0>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&pinctrl_sai2>; 542 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 543 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 544 assigned-clock-rates = <24576000>; 545 status = "okay"; 546}; 547 548&sai3 { 549 pinctrl-names = "default"; 550 pinctrl-0 = <&pinctrl_sai3>; 551 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 552 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 553 assigned-clock-rates = <24576000>; 554 status = "okay"; 555}; 556 557&snvs_pwrkey { 558 status = "okay"; 559}; 560 561&spdif1 { 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_spdif1>; 564 assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; 565 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 566 assigned-clock-rates = <24576000>; 567 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, 568 <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, 569 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 570 <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, 571 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 572 <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; 573 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", 574 "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", 575 "pll8k", "pll11k"; 576 status = "okay"; 577}; 578 579&uart2 { /* console */ 580 pinctrl-names = "default"; 581 pinctrl-0 = <&pinctrl_uart2>; 582 status = "okay"; 583}; 584 585&usbphynop1 { 586 wakeup-source; 587}; 588 589&usbotg1 { 590 dr_mode = "otg"; 591 hnp-disable; 592 srp-disable; 593 adp-disable; 594 usb-role-switch; 595 disable-over-current; 596 samsung,picophy-pre-emp-curr-control = <3>; 597 samsung,picophy-dc-vol-level-adjust = <7>; 598 status = "okay"; 599 600 port { 601 usb1_drd_sw: endpoint { 602 remote-endpoint = <&typec1_dr_sw>; 603 }; 604 }; 605}; 606 607&usdhc2 { 608 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 609 assigned-clock-rates = <200000000>; 610 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 611 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 612 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 613 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 614 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 615 bus-width = <4>; 616 vmmc-supply = <®_usdhc2_vmmc>; 617 status = "okay"; 618}; 619 620&wdog1 { 621 pinctrl-names = "default"; 622 pinctrl-0 = <&pinctrl_wdog>; 623 fsl,ext-reset-output; 624 status = "okay"; 625}; 626 627&pwm1 { 628 pinctrl-names = "default"; 629 pinctrl-0 = <&pinctrl_backlight>; 630 status = "okay"; 631}; 632 633&iomuxc { 634 pinctrl_fec1: fec1grp { 635 fsl,pins = < 636 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 637 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 638 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 639 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 640 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 641 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 642 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 643 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 644 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 645 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 646 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 647 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 648 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 649 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 650 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 651 >; 652 }; 653 654 pinctrl_gpio_led: gpioledgrp { 655 fsl,pins = < 656 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 657 >; 658 }; 659 660 pinctrl_ir: irgrp { 661 fsl,pins = < 662 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f 663 >; 664 }; 665 666 pinctrl_gpio_wlf: gpiowlfgrp { 667 fsl,pins = < 668 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 669 >; 670 }; 671 672 pinctrl_i2c1: i2c1grp { 673 fsl,pins = < 674 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 675 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 676 >; 677 }; 678 679 pinctrl_i2c2: i2c2grp { 680 fsl,pins = < 681 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 682 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 683 >; 684 }; 685 686 pinctrl_i2c3: i2c3grp { 687 fsl,pins = < 688 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 689 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 690 >; 691 }; 692 693 pinctrl_pcie0: pcie0grp { 694 fsl,pins = < 695 MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 696 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 697 >; 698 }; 699 700 pinctrl_pcie0_reg: pcie0reggrp { 701 fsl,pins = < 702 MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 703 >; 704 }; 705 706 pinctrl_pdm: pdmgrp { 707 fsl,pins = < 708 MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 709 MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 710 MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 711 MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 712 MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6 713 MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6 714 MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6 715 >; 716 }; 717 718 pinctrl_pmic: pmicirqgrp { 719 fsl,pins = < 720 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 721 >; 722 }; 723 724 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 725 fsl,pins = < 726 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 727 >; 728 }; 729 730 pinctrl_sai2: sai2grp { 731 fsl,pins = < 732 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 733 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 734 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 735 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 736 >; 737 }; 738 739 pinctrl_sai3: sai3grp { 740 fsl,pins = < 741 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 742 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 743 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 744 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 745 >; 746 }; 747 748 pinctrl_spdif1: spdif1grp { 749 fsl,pins = < 750 MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 751 MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 752 >; 753 }; 754 755 pinctrl_typec1: typec1grp { 756 fsl,pins = < 757 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 758 >; 759 }; 760 761 pinctrl_uart2: uart2grp { 762 fsl,pins = < 763 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 764 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 765 >; 766 }; 767 768 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { 769 fsl,pins = < 770 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 771 >; 772 }; 773 774 pinctrl_usdhc2: usdhc2grp { 775 fsl,pins = < 776 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 777 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 778 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 779 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 780 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 781 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 782 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 783 >; 784 }; 785 786 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 787 fsl,pins = < 788 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 789 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 790 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 791 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 792 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 793 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 794 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 795 >; 796 }; 797 798 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 799 fsl,pins = < 800 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 801 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 802 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 803 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 804 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 805 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 806 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 807 >; 808 }; 809 810 pinctrl_wdog: wdoggrp { 811 fsl,pins = < 812 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 813 >; 814 }; 815 816 pinctrl_backlight: backlightgrp { 817 fsl,pins = < 818 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 819 >; 820 }; 821 822 pinctrl_camera: cameragrp { 823 fsl,pins = < 824 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 825 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 826 MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 827 >; 828 }; 829}; 830