1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 Emtop Embedded Solutions 4 * 5 * Author: Himanshu Bhavani <himanshu.bhavani@siliconsignals.io> 6 * Author: Tarang Raval <tarang.raval@siliconsignals.io> 7 */ 8 9/dts-v1/; 10 11#include "imx8mm-emtop-som.dtsi" 12 13/ { 14 model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1"; 15 compatible = "ees,imx8mm-emtop-baseboard", "ees,imx8mm-emtop-som", 16 "fsl,imx8mm"; 17 18 connector { 19 compatible = "usb-c-connector"; 20 label = "USB-C"; 21 pinctrl-names = "default"; 22 pinctrl-0 = <&pinctrl_usb_otg>; 23 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; 24 25 port { 26 high_speed_ep: endpoint { 27 remote-endpoint = <&usb_hs_ep>; 28 }; 29 }; 30 }; 31 32 leds { 33 compatible = "gpio-leds"; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&pinctrl_gpio_led>; 36 37 led-1 { 38 label = "buzzer"; 39 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 40 default-state = "off"; 41 }; 42 }; 43 44 osc_can: clock-osc-can { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <16000000>; 48 clock-output-names = "osc-can"; 49 }; 50 51 reg_audio: regulator-audio { 52 compatible = "regulator-fixed"; 53 regulator-name = "wm8904_supply"; 54 regulator-min-microvolt = <1800000>; 55 regulator-max-microvolt = <1800000>; 56 regulator-always-on; 57 }; 58 59 reg_wifi_vmmc: regulator-wifi-vmmc { 60 compatible = "regulator-fixed"; 61 regulator-name = "vmmc"; 62 regulator-min-microvolt = <3300000>; 63 regulator-max-microvolt = <3300000>; 64 gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; 65 enable-active-high; 66 startup-delay-us = <100>; 67 off-on-delay-us = <20000>; 68 }; 69 70 sound-wm8904 { 71 compatible = "simple-audio-card"; 72 simple-audio-card,bitclock-master = <&dailink_master>; 73 simple-audio-card,format = "i2s"; 74 simple-audio-card,frame-master = <&dailink_master>; 75 simple-audio-card,name = "wm8904-audio"; 76 simple-audio-card,mclk-fs = <256>; 77 simple-audio-card,routing = 78 "Headphone Jack", "HPOUTL", 79 "Headphone Jack", "HPOUTR", 80 "IN2L", "Line In Jack", 81 "IN2R", "Line In Jack", 82 "Headphone Jack", "MICBIAS", 83 "IN1L", "Headphone Jack"; 84 85 simple-audio-card,widgets = 86 "Microphone","Headphone Jack", 87 "Headphone", "Headphone Jack", 88 "Line", "Line In Jack"; 89 90 dailink_master: simple-audio-card,codec { 91 sound-dai = <&wm8904>; 92 }; 93 94 simple-audio-card,cpu { 95 sound-dai = <&sai3>; 96 }; 97 }; 98 99 sound-spdif { 100 compatible = "fsl,imx-audio-spdif"; 101 model = "imx-spdif"; 102 spdif-controller = <&spdif1>; 103 spdif-out; 104 spdif-in; 105 }; 106}; 107 108/* CAN BUS */ 109&ecspi2 { 110 pinctrl-names = "default"; 111 pinctrl-0 = <&pinctrl_ecspi2>; 112 status = "okay"; 113 114 can: can@0 { 115 compatible = "microchip,mcp2515"; 116 reg = <0>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_canbus>; 119 clocks = <&osc_can>; 120 interrupt-parent = <&gpio1>; 121 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; 122 spi-max-frequency = <10000000>; 123 }; 124}; 125 126&fec1 { 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_fec1>; 129 phy-mode = "rgmii-id"; 130 phy-handle = <ðphy0>; 131 fsl,magic-packet; 132 status = "okay"; 133 134 mdio { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 ethphy0: ethernet-phy@4 { 139 compatible = "ethernet-phy-ieee802.3-c22"; 140 reg = <4>; 141 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 142 reset-assert-us = <10000>; 143 vddio-supply = <&vddio>; 144 145 vddio: vddio-regulator { 146 regulator-min-microvolt = <1800000>; 147 regulator-max-microvolt = <1800000>; 148 }; 149 }; 150 }; 151}; 152 153&i2c3 { 154 clock-frequency = <100000>; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_i2c3>; 157 status = "okay"; 158 159 wm8904: audio-codec@1a { 160 compatible = "wlf,wm8904"; 161 reg = <0x1a>; 162 #sound-dai-cells = <0>; 163 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 164 clock-names = "mclk"; 165 DCVDD-supply = <®_audio>; 166 DBVDD-supply = <®_audio>; 167 AVDD-supply = <®_audio>; 168 CPVDD-supply = <®_audio>; 169 MICVDD-supply = <®_audio>; 170 }; 171 172 rtc@32 { 173 compatible = "epson,rx8025"; 174 reg = <0x32>; 175 }; 176}; 177 178/* AUDIO */ 179&sai3 { 180 pinctrl-names = "default"; 181 pinctrl-0 = <&pinctrl_sai3>; 182 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 183 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 184 assigned-clock-rates = <24576000>; 185 status = "okay"; 186}; 187 188&spdif1 { 189 pinctrl-names = "default"; 190 pinctrl-0 = <&pinctrl_spdif1>; 191 assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; 192 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 193 assigned-clock-rates = <24576000>; 194 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, 195 <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, 196 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 197 <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, 198 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 199 <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; 200 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", 201 "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; 202 status = "okay"; 203}; 204 205/* USBOTG */ 206&usbotg1 { 207 dr_mode = "otg"; 208 usb-role-switch; 209 status = "okay"; 210 211 port { 212 usb_hs_ep: endpoint { 213 remote-endpoint = <&high_speed_ep>; 214 }; 215 }; 216}; 217 218&usbotg2 { 219 dr_mode = "host"; 220 status = "okay"; 221}; 222 223/* Wifi */ 224&usdhc1 { 225 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 226 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 227 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 228 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 229 bus-width = <4>; 230 vmmc-supply = <®_wifi_vmmc>; 231 cap-power-off-card; 232 keep-power-in-suspend; 233 non-removable; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 status = "okay"; 237 238 wifi: wifi@1 { 239 compatible = "brcm,bcm4329-fmac"; 240 reg = <1>; 241 interrupt-parent = <&gpio2>; 242 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; 243 interrupt-names = "host-wake"; 244 }; 245}; 246 247/* SD-card */ 248&usdhc2 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_usdhc2>; 251 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 252 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 253 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 254 bus-width = <4>; 255 status = "okay"; 256}; 257 258&iomuxc { 259 260 pinctrl_canbus: canbusgrp { 261 fsl,pins = < 262 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x14 263 >; 264 }; 265 266 pinctrl_ecspi2: ecspi2grp { 267 fsl,pins = < 268 MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82 269 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 270 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 271 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 272 >; 273 }; 274 275 pinctrl_usb_otg: usbotggrp { 276 fsl,pins = < 277 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 /* otg_id */ 278 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* otg_vbus */ 279 >; 280 }; 281 282 pinctrl_fec1: fec1grp { 283 fsl,pins = < 284 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 285 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 286 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 287 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 288 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 289 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 290 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 291 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 292 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 293 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 294 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 295 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 296 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 297 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 298 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 299 >; 300 }; 301 302 pinctrl_i2c3: i2c3grp { 303 fsl,pins = < 304 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 305 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 306 >; 307 }; 308 309 pinctrl_sai3: sai3grp { 310 fsl,pins = < 311 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 312 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 313 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 314 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 315 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 316 >; 317 }; 318 319 pinctrl_spdif1: spdif1grp { 320 fsl,pins = < 321 MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 322 >; 323 }; 324 325 pinctrl_usdhc1: usdhc1grp { 326 fsl,pins = < 327 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 328 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 329 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 330 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 331 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 332 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 333 >; 334 }; 335 336 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp{ 337 fsl,pins = < 338 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 339 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 340 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 341 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 342 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 343 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 344 >; 345 }; 346 347 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 348 fsl,pins = < 349 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 350 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 351 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 352 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 353 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 354 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 355 >; 356 }; 357 358 pinctrl_usdhc1_gpio: usdhc1-gpiogrp { 359 fsl,pins = < 360 MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 /* wl_reg_on */ 361 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 /* wl_host_wake */ 362 MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */ 363 >; 364 }; 365 366 pinctrl_usdhc2: usdhc2grp { 367 fsl,pins = < 368 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 369 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 370 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 371 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 372 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 373 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 374 >; 375 }; 376 377 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 378 fsl,pins = < 379 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 380 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 381 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 382 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 383 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 384 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 385 >; 386 }; 387 388 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 389 fsl,pins = < 390 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 391 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 392 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 393 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 394 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 395 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 396 >; 397 }; 398}; 399