1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Copyright 2018 NXP 4// Copyright (C) 2021 emtrion GmbH 5// 6 7/dts-v1/; 8 9#include "imx8mm.dtsi" 10 11/ { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 som_leds: leds { 17 compatible = "gpio-leds"; 18 pinctrl-names = "default"; 19 pinctrl-0 = <&pinctrl_gpio_led>; 20 21 led-green { 22 label = "som:green"; 23 gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; 24 default-state = "on"; 25 linux,default-trigger = "heartbeat"; 26 }; 27 28 led-red { 29 label = "som:red"; 30 gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; 31 default-state = "off"; 32 }; 33 }; 34 35 lvds_backlight: lvds-backlight { 36 compatible = "pwm-backlight"; 37 enable-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; 38 pwms = <&pwm1 0 50000 0>; 39 brightness-levels = < 40 0 4 8 16 32 64 80 96 112 41 128 144 160 176 250 42 >; 43 default-brightness-level = <9>; 44 status = "disabled"; 45 }; 46 47 reg_usdhc1_vmmc: regulator-emmc { 48 compatible = "regulator-fixed"; 49 regulator-name = "eMMC"; 50 regulator-min-microvolt = <3300000>; 51 regulator-max-microvolt = <3300000>; 52 }; 53 54 reg_usdhc2_vmmc: regulator-usdhc2 { 55 compatible = "regulator-fixed"; 56 regulator-name = "sdcard_3V3"; 57 regulator-min-microvolt = <3300000>; 58 regulator-max-microvolt = <3300000>; 59 }; 60}; 61 62&A53_0 { 63 cpu-supply = <&buck2_reg>; 64}; 65 66&ecspi1 { 67 pinctrl-names = "default"; 68 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 69 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, 70 <&gpio5 13 GPIO_ACTIVE_LOW>; 71 status = "okay"; 72}; 73 74&fec1 { 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_fec1>; 77 phy-mode = "rgmii-id"; 78 phy-handle = <ðphy0>; 79 fsl,magic-packet; 80 status = "okay"; 81 82 mdio { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 ethphy0: ethernet-phy@0 { 87 compatible = "ethernet-phy-ieee802.3-c22"; 88 reg = <0>; 89 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 90 reset-assert-us = <10000>; 91 }; 92 }; 93}; 94 95&flexspi { 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_flexspi0>; 98 pinctrl-1 = <&pinctrl_flexspi1>; 99 status = "okay"; 100 101 flash0: flash@0 { 102 reg = <0>; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 compatible = "jedec,spi-nor"; 106 spi-max-frequency = <40000000>; 107 }; 108}; 109 110&iomuxc { 111 pinctrl_csi_pwn: csi-pwn-grp { 112 fsl,pins = < 113 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 114 >; 115 }; 116 117 pinctrl_ecspi1: ecspi1-grp { 118 fsl,pins = < 119 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 120 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 121 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 122 >; 123 }; 124 125 pinctrl_ecspi1_cs: ecspi1cs-grp { 126 fsl,pins = < 127 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 128 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 129 >; 130 }; 131 132 pinctrl_fec1: fec1-grp { 133 fsl,pins = < 134 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 135 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 136 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 137 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 138 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 139 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 140 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 141 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 142 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 143 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 144 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 145 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 146 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 147 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 148 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 149 >; 150 }; 151 152 pinctrl_flexspi0: flexspi0-grp { 153 fsl,pins = < 154 MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 155 MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 156 MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 157 MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 158 MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 159 MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 160 MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 161 >; 162 }; 163 164 pinctrl_flexspi1: flexspi1-grp { 165 fsl,pins = < 166 MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c2 167 MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 168 MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 169 MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 170 MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 171 MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 172 >; 173 }; 174 175 pinctrl_gpio_led: gpio-led-grp { 176 fsl,pins = < 177 MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 178 MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 179 >; 180 }; 181 182 pinctrl_i2c1: i2c1-grp { 183 fsl,pins = < 184 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 185 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 186 >; 187 }; 188 189 pinctrl_i2c2: i2c2grp { 190 fsl,pins = < 191 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 192 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 193 >; 194 }; 195 196 pinctrl_i2c3: i2c3-grp { 197 fsl,pins = < 198 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 199 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 200 >; 201 }; 202 203 pinctrl_lvds: lvds-grp { 204 fsl,pins = < 205 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x06 206 >; 207 }; 208 209 pinctrl_pcie0: pcie0-grp { 210 fsl,pins = < 211 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 212 MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x41 213 >; 214 }; 215 216 pinctrl_pmic: pmicirq-grp { 217 fsl,pins = < 218 MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41 219 >; 220 }; 221 222 pinctrl_pwm1: pwm1-grp { 223 fsl,pins = < 224 MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 225 >; 226 }; 227 228 pinctrl_sai2: sai2-grp { 229 fsl,pins = < 230 MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 231 MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 232 MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 233 MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 234 MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 235 MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 236 MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 237 >; 238 }; 239 240 pinctrl_spdif1: spdif1-grp { 241 fsl,pins = < 242 MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 243 MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 244 >; 245 }; 246 247 pinctrl_uart1: uart1-grp { 248 fsl,pins = < 249 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 250 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 251 >; 252 }; 253 254 pinctrl_uart2: uart2-grp { 255 fsl,pins = < 256 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 257 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 258 259 /* rts and cts */ 260 MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 261 MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 262 >; 263 }; 264 265 pinctrl_uart3: uart3-grp { 266 fsl,pins = < 267 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 268 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 269 >; 270 }; 271 272 pinctrl_uart4: uart4-grp { 273 fsl,pins = < 274 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 275 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 276 >; 277 }; 278 279 pinctrl_usdhc1: usdhc1-grp { 280 fsl,pins = < 281 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 282 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 283 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 284 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 285 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 286 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 287 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 288 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 289 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 290 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 291 >; 292 }; 293 294 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 295 fsl,pins = < 296 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 297 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 298 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 299 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 300 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 301 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 302 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 303 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 304 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 305 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 306 >; 307 }; 308 309 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 310 fsl,pins = < 311 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 312 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 313 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 314 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 315 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 316 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 317 MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 318 MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 319 MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 320 MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 321 >; 322 }; 323 324 pinctrl_usdhc1_gpio: usdhc1-gpio-grp { 325 fsl,pins = < 326 MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x41 327 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c4 328 >; 329 }; 330 331 pinctrl_usdhc2: usdhc2-grp { 332 fsl,pins = < 333 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 334 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 335 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 336 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 337 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 338 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 339 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 340 >; 341 }; 342 343 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { 344 fsl,pins = < 345 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 346 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 347 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 348 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 349 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 350 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 351 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 352 >; 353 }; 354 355 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { 356 fsl,pins = < 357 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 358 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 359 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 360 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 361 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 362 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 363 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 364 >; 365 }; 366 367 /* no reset for sdhc2 interface */ 368 pinctrl_usdhc2_gpio: usdhc2-gpio-grp { 369 fsl,pins = < 370 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 371 MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x1c4 372 >; 373 }; 374 375 pinctrl_wdog: wdog-grp { 376 fsl,pins = < 377 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 378 >; 379 }; 380}; 381 382&i2c1 { 383 clock-frequency = <400000>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_i2c1>; 386 status = "okay"; 387}; 388 389&i2c2 { 390 clock-frequency = <400000>; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pinctrl_i2c2>; 393 status = "okay"; 394}; 395 396&i2c3 { 397 clock-frequency = <400000>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&pinctrl_i2c3>; 400 status = "okay"; 401 402 bd71847: pmic@4b { 403 compatible = "rohm,bd71847"; 404 reg = <0x4b>; 405 pinctrl-0 = <&pinctrl_pmic>; 406 interrupt-parent = <&gpio3>; 407 interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 408 rohm,reset-snvs-powered; 409 410 regulators { 411 buck1_reg: BUCK1 { 412 regulator-name = "buck1"; 413 regulator-min-microvolt = <700000>; 414 regulator-max-microvolt = <1300000>; 415 regulator-boot-on; 416 regulator-always-on; 417 regulator-ramp-delay = <1250>; 418 }; 419 420 buck2_reg: BUCK2 { 421 regulator-name = "buck2"; 422 regulator-min-microvolt = <700000>; 423 regulator-max-microvolt = <1300000>; 424 regulator-boot-on; 425 regulator-always-on; 426 regulator-ramp-delay = <1250>; 427 rohm,dvs-run-voltage = <1000000>; 428 rohm,dvs-idle-voltage = <900000>; 429 }; 430 431 buck3_reg: BUCK3 { 432 // BUCK5 in datasheet 433 regulator-name = "buck3"; 434 regulator-min-microvolt = <700000>; 435 regulator-max-microvolt = <1350000>; 436 regulator-boot-on; 437 regulator-always-on; 438 }; 439 440 buck4_reg: BUCK4 { 441 // BUCK6 in datasheet 442 regulator-name = "buck4"; 443 regulator-min-microvolt = <3000000>; 444 regulator-max-microvolt = <3300000>; 445 regulator-boot-on; 446 regulator-always-on; 447 }; 448 449 buck5_reg: BUCK5 { 450 // BUCK7 in datasheet 451 regulator-name = "buck5"; 452 regulator-min-microvolt = <1605000>; 453 regulator-max-microvolt = <1995000>; 454 regulator-boot-on; 455 regulator-always-on; 456 }; 457 458 buck6_reg: BUCK6 { 459 // BUCK8 in datasheet 460 regulator-name = "buck6"; 461 regulator-min-microvolt = <800000>; 462 regulator-max-microvolt = <1400000>; 463 regulator-boot-on; 464 regulator-always-on; 465 }; 466 467 ldo1_reg: LDO1 { 468 regulator-name = "ldo1"; 469 regulator-min-microvolt = <1600000>; 470 regulator-max-microvolt = <1900000>; 471 regulator-boot-on; 472 regulator-always-on; 473 }; 474 475 ldo2_reg: LDO2 { 476 regulator-name = "ldo2"; 477 regulator-min-microvolt = <800000>; 478 regulator-max-microvolt = <900000>; 479 regulator-boot-on; 480 regulator-always-on; 481 }; 482 483 ldo3_reg: LDO3 { 484 regulator-name = "ldo3"; 485 regulator-min-microvolt = <1800000>; 486 regulator-max-microvolt = <3300000>; 487 regulator-boot-on; 488 regulator-always-on; 489 }; 490 491 ldo4_reg: LDO4 { 492 regulator-name = "ldo4"; 493 regulator-min-microvolt = <900000>; 494 regulator-max-microvolt = <1800000>; 495 regulator-boot-on; 496 regulator-always-on; 497 }; 498 499 ldo6_reg: LDO6 { 500 regulator-name = "ldo6"; 501 regulator-min-microvolt = <900000>; 502 regulator-max-microvolt = <1800000>; 503 regulator-boot-on; 504 regulator-always-on; 505 }; 506 }; 507 }; 508 509 rv1805: rtc@69 { 510 compatible = "abracon,ab1805"; 511 reg = <0x69>; 512 }; 513}; 514 515&mu { 516 status = "okay"; 517}; 518 519&pwm1 { 520 pinctrl-names = "default"; 521 pinctrl-0 = <&pinctrl_pwm1>; 522}; 523 524&sai2 { 525 #sound-dai-cells = <0>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&pinctrl_sai2>; 528 assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 529 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 530 assigned-clock-rates = <12000000>; 531 status = "disabled"; 532}; 533 534&spdif1 { 535 pinctrl-names = "default"; 536 pinctrl-0 = <&pinctrl_spdif1>; 537 assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; 538 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 539 assigned-clock-rates = <24576000>; 540 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, 541 <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, 542 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 543 <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, 544 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, 545 <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; 546 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", 547 "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; 548 status = "disabled"; 549}; 550 551&uart1 { /* console */ 552 pinctrl-names = "default"; 553 pinctrl-0 = <&pinctrl_uart1>; 554 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 555 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 556 status = "okay"; 557}; 558 559&uart2 { 560 pinctrl-names = "default"; 561 pinctrl-0 = <&pinctrl_uart2>; 562 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 563 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 564 status = "okay"; 565}; 566 567&uart3 { 568 pinctrl-names = "default"; 569 pinctrl-0 = <&pinctrl_uart3>; 570 assigned-clocks = <&clk IMX8MM_CLK_UART3>; 571 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 572 status = "okay"; 573}; 574 575&uart4 { 576 pinctrl-names = "default"; 577 pinctrl-0 = <&pinctrl_uart4>; 578 assigned-clocks = <&clk IMX8MM_CLK_UART4>; 579 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 580 status = "okay"; 581}; 582 583&usbotg1 { 584 dr_mode = "otg"; 585 over-current-active-low; 586 status = "okay"; 587}; 588 589&usbotg2 { 590 dr_mode = "host"; 591 disable-over-current; 592 status = "disabled"; 593}; 594 595&usdhc1 { 596 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 597 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 598 pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 599 pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 600 bus-width = <8>; 601 vmmc-supply = <®_usdhc1_vmmc>; 602 keep-power-in-suspend; 603 non-removable; 604 status = "okay"; 605}; 606 607&usdhc2 { 608 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 609 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 610 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 611 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 612 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 613 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 614 bus-width = <4>; 615 vmmc-supply = <®_usdhc2_vmmc>; 616 no-1-8-v; 617 status = "okay"; 618}; 619 620&wdog1 { 621 pinctrl-names = "default"; 622 pinctrl-0 = <&pinctrl_wdog>; 623 fsl,ext-reset-output; 624 status = "okay"; 625}; 626