1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2020 Compass Electronics Group, LLC 4 */ 5 6/ { 7 leds { 8 compatible = "gpio-leds"; 9 10 led0 { 11 label = "gen_led0"; 12 gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>; 13 default-state = "off"; 14 }; 15 16 led1 { 17 label = "gen_led1"; 18 gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>; 19 default-state = "off"; 20 }; 21 22 led2 { 23 label = "gen_led2"; 24 gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>; 25 default-state = "off"; 26 }; 27 28 led3 { 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_led3>; 31 label = "heartbeat"; 32 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 33 linux,default-trigger = "heartbeat"; 34 }; 35 }; 36 37 reg_audio: regulator-audio { 38 compatible = "regulator-fixed"; 39 regulator-name = "3v3_aud"; 40 regulator-min-microvolt = <3300000>; 41 regulator-max-microvolt = <3300000>; 42 gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>; 43 enable-active-high; 44 }; 45 46 reg_usdhc2_vmmc: regulator-usdhc2 { 47 compatible = "regulator-fixed"; 48 regulator-name = "VSD_3V3"; 49 regulator-min-microvolt = <3300000>; 50 regulator-max-microvolt = <3300000>; 51 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 }; 54 55 sound { 56 compatible = "fsl,imx-audio-wm8962"; 57 model = "wm8962-audio"; 58 audio-cpu = <&sai3>; 59 audio-codec = <&wm8962>; 60 audio-routing = 61 "Headphone Jack", "HPOUTL", 62 "Headphone Jack", "HPOUTR", 63 "Ext Spk", "SPKOUTL", 64 "Ext Spk", "SPKOUTR", 65 "AMIC", "MICBIAS", 66 "IN3R", "AMIC"; 67 }; 68}; 69 70&ecspi2 { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_espi2>; 73 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 74 status = "okay"; 75 76 eeprom@0 { 77 compatible = "microchip,at25160bn", "atmel,at25"; 78 reg = <0>; 79 spi-max-frequency = <5000000>; 80 spi-cpha; 81 spi-cpol; 82 pagesize = <32>; 83 size = <2048>; 84 address-width = <16>; 85 }; 86}; 87 88&i2c2 { 89 clock-frequency = <400000>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_i2c2>; 92 status = "okay"; 93}; 94 95&i2c4 { 96 clock-frequency = <400000>; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_i2c4>; 99 status = "okay"; 100 101 wm8962: audio-codec@1a { 102 compatible = "wlf,wm8962"; 103 reg = <0x1a>; 104 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; 105 DCVDD-supply = <®_audio>; 106 DBVDD-supply = <®_audio>; 107 AVDD-supply = <®_audio>; 108 CPVDD-supply = <®_audio>; 109 MICVDD-supply = <®_audio>; 110 PLLVDD-supply = <®_audio>; 111 SPKVDD1-supply = <®_audio>; 112 SPKVDD2-supply = <®_audio>; 113 gpio-cfg = < 114 0x0000 /* 0:Default */ 115 0x0000 /* 1:Default */ 116 0x0000 /* 2:FN_DMICCLK */ 117 0x0000 /* 3:Default */ 118 0x0000 /* 4:FN_DMICCDAT */ 119 0x0000 /* 5:Default */ 120 >; 121 }; 122 123 pca6416_0: gpio@20 { 124 compatible = "nxp,pcal6416"; 125 reg = <0x20>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_pcal6414>; 128 gpio-controller; 129 #gpio-cells = <2>; 130 interrupt-parent = <&gpio4>; 131 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 132 }; 133 134 pca6416_1: gpio@21 { 135 compatible = "nxp,pcal6416"; 136 reg = <0x21>; 137 gpio-controller; 138 #gpio-cells = <2>; 139 interrupt-parent = <&gpio4>; 140 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 141 }; 142}; 143 144&sai3 { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_sai3>; 147 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 148 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 149 assigned-clock-rates = <24576000>; 150 fsl,sai-mclk-direction-output; 151 status = "okay"; 152}; 153 154&snvs_pwrkey { 155 status = "okay"; 156}; 157 158&uart2 { /* console */ 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_uart2>; 161 status = "okay"; 162}; 163 164&uart3 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_uart3>; 167 assigned-clocks = <&clk IMX8MM_CLK_UART3>; 168 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 169 status = "okay"; 170}; 171 172&usdhc2 { 173 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 174 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 175 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 176 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 177 bus-width = <4>; 178 vmmc-supply = <®_usdhc2_vmmc>; 179 status = "okay"; 180}; 181 182&iomuxc { 183 pinctrl_espi2: espi2grp { 184 fsl,pins = < 185 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 186 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 187 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 188 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41 189 >; 190 }; 191 192 pinctrl_i2c2: i2c2grp { 193 fsl,pins = < 194 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 195 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 196 >; 197 }; 198 199 pinctrl_i2c4: i2c4grp { 200 fsl,pins = < 201 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 202 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 203 >; 204 }; 205 206 pinctrl_led3: led3grp { 207 fsl,pins = < 208 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41 209 >; 210 }; 211 212 pinctrl_pcal6414: pcal6414-gpiogrp { 213 fsl,pins = < 214 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 215 >; 216 }; 217 218 pinctrl_sai3: sai3grp { 219 fsl,pins = < 220 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 221 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 222 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 223 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 224 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 225 >; 226 }; 227 228 pinctrl_uart2: uart2grp { 229 fsl,pins = < 230 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 231 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 232 >; 233 }; 234 235 pinctrl_uart3: uart3grp { 236 fsl,pins = < 237 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 238 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 239 >; 240 }; 241 242 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 243 fsl,pins = < 244 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41 245 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 246 >; 247 }; 248 249 pinctrl_usdhc2: usdhc2grp { 250 fsl,pins = < 251 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 252 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 253 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 254 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 255 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 256 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 257 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 258 >; 259 }; 260 261 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 262 fsl,pins = < 263 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 264 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 265 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 266 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 267 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 268 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 269 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 270 >; 271 }; 272 273 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 274 fsl,pins = < 275 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 276 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 277 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 278 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 279 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 280 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 281 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 282 >; 283 }; 284}; 285