1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx8-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/clock/imx8-lpcg.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/pinctrl/pads-imx8dxl.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 ethernet1 = &eqos; 24 gpio0 = &lsio_gpio0; 25 gpio1 = &lsio_gpio1; 26 gpio2 = &lsio_gpio2; 27 gpio3 = &lsio_gpio3; 28 gpio4 = &lsio_gpio4; 29 gpio5 = &lsio_gpio5; 30 gpio6 = &lsio_gpio6; 31 gpio7 = &lsio_gpio7; 32 mu1 = &lsio_mu1; 33 }; 34 35 cpus: cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 /* We have 1 clusters with 2 Cortex-A35 cores */ 40 A35_0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35"; 43 reg = <0x0 0x0>; 44 enable-method = "psci"; 45 next-level-cache = <&A35_L2>; 46 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 47 #cooling-cells = <2>; 48 operating-points-v2 = <&a35_opp_table>; 49 }; 50 51 A35_1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a35"; 54 reg = <0x0 0x1>; 55 enable-method = "psci"; 56 next-level-cache = <&A35_L2>; 57 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 58 #cooling-cells = <2>; 59 operating-points-v2 = <&a35_opp_table>; 60 }; 61 62 A35_L2: l2-cache0 { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 }; 67 }; 68 69 a35_opp_table: opp-table { 70 compatible = "operating-points-v2"; 71 opp-shared; 72 73 opp-900000000 { 74 opp-hz = /bits/ 64 <900000000>; 75 opp-microvolt = <1000000>; 76 clock-latency-ns = <150000>; 77 }; 78 79 opp-1200000000 { 80 opp-hz = /bits/ 64 <1200000000>; 81 opp-microvolt = <1100000>; 82 clock-latency-ns = <150000>; 83 opp-suspend; 84 }; 85 }; 86 87 gic: interrupt-controller@51a00000 { 88 compatible = "arm,gic-v3"; 89 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 90 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 91 #interrupt-cells = <3>; 92 interrupt-controller; 93 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 94 }; 95 96 reserved-memory { 97 #address-cells = <2>; 98 #size-cells = <2>; 99 ranges; 100 101 dsp_reserved: dsp@92400000 { 102 reg = <0 0x92400000 0 0x2000000>; 103 no-map; 104 }; 105 }; 106 107 pmu { 108 compatible = "arm,cortex-a35-pmu"; 109 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 110 }; 111 112 psci { 113 compatible = "arm,psci-1.0"; 114 method = "smc"; 115 }; 116 117 system-controller { 118 compatible = "fsl,imx-scu"; 119 mbox-names = "tx0", 120 "rx0", 121 "gip3"; 122 mboxes = <&lsio_mu1 0 0 123 &lsio_mu1 1 0 124 &lsio_mu1 3 3>; 125 126 pd: power-controller { 127 compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd"; 128 #power-domain-cells = <1>; 129 }; 130 131 clk: clock-controller { 132 compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; 133 #clock-cells = <2>; 134 }; 135 136 scu_gpio: gpio { 137 compatible = "fsl,imx8qxp-sc-gpio"; 138 gpio-controller; 139 #gpio-cells = <2>; 140 }; 141 142 iomuxc: pinctrl { 143 compatible = "fsl,imx8dxl-iomuxc"; 144 }; 145 146 ocotp: ocotp { 147 compatible = "fsl,imx8qxp-scu-ocotp"; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 151 fec_mac0: mac@2c4 { 152 reg = <0x2c4 6>; 153 }; 154 155 fec_mac1: mac@2c6 { 156 reg = <0x2c6 6>; 157 }; 158 }; 159 160 rtc: rtc { 161 compatible = "fsl,imx8qxp-sc-rtc"; 162 }; 163 164 sc_pwrkey: keys { 165 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 166 linux,keycodes = <KEY_POWER>; 167 wakeup-source; 168 }; 169 170 watchdog { 171 compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt"; 172 timeout-sec = <60>; 173 }; 174 175 tsens: thermal-sensor { 176 compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal"; 177 #thermal-sensor-cells = <1>; 178 }; 179 }; 180 181 timer { 182 compatible = "arm,armv8-timer"; 183 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 184 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 185 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 186 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 187 }; 188 189 thermal_zones: thermal-zones { 190 cpu-thermal { 191 polling-delay-passive = <250>; 192 polling-delay = <2000>; 193 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 194 195 trips { 196 cpu_alert0: trip0 { 197 temperature = <107000>; 198 hysteresis = <2000>; 199 type = "passive"; 200 }; 201 cpu_crit0: trip1 { 202 temperature = <127000>; 203 hysteresis = <2000>; 204 type = "critical"; 205 }; 206 }; 207 208 cooling-maps { 209 map0 { 210 trip = <&cpu_alert0>; 211 cooling-device = 212 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 213 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 214 }; 215 }; 216 }; 217 }; 218 219 /* The two values below cannot be changed by the board */ 220 xtal32k: clock-xtal32k { 221 compatible = "fixed-clock"; 222 #clock-cells = <0>; 223 clock-frequency = <32768>; 224 clock-output-names = "xtal_32KHz"; 225 }; 226 227 xtal24m: clock-xtal24m { 228 compatible = "fixed-clock"; 229 #clock-cells = <0>; 230 clock-frequency = <24000000>; 231 clock-output-names = "xtal_24MHz"; 232 }; 233 234 /* sorted in register address */ 235 #include "imx8-ss-cm40.dtsi" 236 #include "imx8-ss-adma.dtsi" 237 #include "imx8-ss-conn.dtsi" 238 #include "imx8-ss-ddr.dtsi" 239 #include "imx8-ss-lsio.dtsi" 240}; 241 242#include "imx8dxl-ss-adma.dtsi" 243#include "imx8dxl-ss-conn.dtsi" 244#include "imx8dxl-ss-lsio.dtsi" 245#include "imx8dxl-ss-ddr.dtsi" 246 247&cm40_intmux { 248 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 256}; 257