1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx8-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/clock/imx8-lpcg.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/pinctrl/pads-imx8dxl.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 ethernet1 = &eqos; 24 gpio0 = &lsio_gpio0; 25 gpio1 = &lsio_gpio1; 26 gpio2 = &lsio_gpio2; 27 gpio3 = &lsio_gpio3; 28 gpio4 = &lsio_gpio4; 29 gpio5 = &lsio_gpio5; 30 gpio6 = &lsio_gpio6; 31 gpio7 = &lsio_gpio7; 32 mu1 = &lsio_mu1; 33 spi0 = &lpspi0; 34 spi1 = &lpspi1; 35 spi2 = &lpspi2; 36 spi3 = &lpspi3; 37 }; 38 39 cpus: cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 /* We have 1 clusters with 2 Cortex-A35 cores */ 44 A35_0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&A35_L2>; 50 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 51 #cooling-cells = <2>; 52 operating-points-v2 = <&a35_opp_table>; 53 }; 54 55 A35_1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35"; 58 reg = <0x0 0x1>; 59 enable-method = "psci"; 60 next-level-cache = <&A35_L2>; 61 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 62 #cooling-cells = <2>; 63 operating-points-v2 = <&a35_opp_table>; 64 }; 65 66 A35_L2: l2-cache0 { 67 compatible = "cache"; 68 cache-level = <2>; 69 cache-unified; 70 }; 71 }; 72 73 a35_opp_table: opp-table { 74 compatible = "operating-points-v2"; 75 opp-shared; 76 77 opp-900000000 { 78 opp-hz = /bits/ 64 <900000000>; 79 opp-microvolt = <1000000>; 80 clock-latency-ns = <150000>; 81 }; 82 83 opp-1200000000 { 84 opp-hz = /bits/ 64 <1200000000>; 85 opp-microvolt = <1100000>; 86 clock-latency-ns = <150000>; 87 opp-suspend; 88 }; 89 }; 90 91 gic: interrupt-controller@51a00000 { 92 compatible = "arm,gic-v3"; 93 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 94 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 95 #interrupt-cells = <3>; 96 interrupt-controller; 97 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 98 }; 99 100 reserved-memory { 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 dsp_reserved: dsp@92400000 { 106 reg = <0 0x92400000 0 0x2000000>; 107 no-map; 108 }; 109 }; 110 111 pmu { 112 compatible = "arm,cortex-a35-pmu"; 113 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 114 }; 115 116 psci { 117 compatible = "arm,psci-1.0"; 118 method = "smc"; 119 }; 120 121 system-controller { 122 compatible = "fsl,imx-scu"; 123 mbox-names = "tx0", 124 "rx0", 125 "gip3"; 126 mboxes = <&lsio_mu1 0 0 127 &lsio_mu1 1 0 128 &lsio_mu1 3 3>; 129 130 pd: power-controller { 131 compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd"; 132 #power-domain-cells = <1>; 133 }; 134 135 clk: clock-controller { 136 compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; 137 #clock-cells = <2>; 138 }; 139 140 scu_gpio: gpio { 141 compatible = "fsl,imx8qxp-sc-gpio"; 142 gpio-controller; 143 #gpio-cells = <2>; 144 }; 145 146 iomuxc: pinctrl { 147 compatible = "fsl,imx8dxl-iomuxc"; 148 }; 149 150 ocotp: ocotp { 151 compatible = "fsl,imx8qxp-scu-ocotp"; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 155 fec_mac0: mac@2c4 { 156 reg = <0x2c4 6>; 157 }; 158 159 fec_mac1: mac@2c6 { 160 reg = <0x2c6 6>; 161 }; 162 }; 163 164 rtc: rtc { 165 compatible = "fsl,imx8qxp-sc-rtc"; 166 }; 167 168 sc_pwrkey: keys { 169 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 170 linux,keycodes = <KEY_POWER>; 171 wakeup-source; 172 }; 173 174 watchdog { 175 compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt"; 176 timeout-sec = <60>; 177 }; 178 179 tsens: thermal-sensor { 180 compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal"; 181 #thermal-sensor-cells = <1>; 182 }; 183 }; 184 185 timer { 186 compatible = "arm,armv8-timer"; 187 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 188 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 189 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 190 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 191 }; 192 193 thermal_zones: thermal-zones { 194 cpu-thermal { 195 polling-delay-passive = <250>; 196 polling-delay = <2000>; 197 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 198 199 trips { 200 cpu_alert0: trip0 { 201 temperature = <107000>; 202 hysteresis = <2000>; 203 type = "passive"; 204 }; 205 cpu_crit0: trip1 { 206 temperature = <127000>; 207 hysteresis = <2000>; 208 type = "critical"; 209 }; 210 }; 211 212 cooling-maps { 213 map0 { 214 trip = <&cpu_alert0>; 215 cooling-device = 216 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 217 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 218 }; 219 }; 220 }; 221 }; 222 223 /* The two values below cannot be changed by the board */ 224 xtal32k: clock-xtal32k { 225 compatible = "fixed-clock"; 226 #clock-cells = <0>; 227 clock-frequency = <32768>; 228 clock-output-names = "xtal_32KHz"; 229 }; 230 231 xtal24m: clock-xtal24m { 232 compatible = "fixed-clock"; 233 #clock-cells = <0>; 234 clock-frequency = <24000000>; 235 clock-output-names = "xtal_24MHz"; 236 }; 237 238 /* sorted in register address */ 239 #include "imx8-ss-cm40.dtsi" 240 #include "imx8-ss-adma.dtsi" 241 #include "imx8-ss-conn.dtsi" 242 #include "imx8-ss-ddr.dtsi" 243 #include "imx8-ss-lsio.dtsi" 244 #include "imx8-ss-hsio.dtsi" 245}; 246 247#include "imx8dxl-ss-adma.dtsi" 248#include "imx8dxl-ss-conn.dtsi" 249#include "imx8dxl-ss-lsio.dtsi" 250#include "imx8dxl-ss-ddr.dtsi" 251#include "imx8dxl-ss-hsio.dtsi" 252 253&cm40_intmux { 254 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 262}; 263