1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx8-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/pinctrl/pads-imx8dxl.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet0 = &fec1; 22 ethernet1 = &eqos; 23 gpio0 = &lsio_gpio0; 24 gpio1 = &lsio_gpio1; 25 gpio2 = &lsio_gpio2; 26 gpio3 = &lsio_gpio3; 27 gpio4 = &lsio_gpio4; 28 gpio5 = &lsio_gpio5; 29 gpio6 = &lsio_gpio6; 30 gpio7 = &lsio_gpio7; 31 mu1 = &lsio_mu1; 32 }; 33 34 cpus: cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 /* We have 1 clusters with 2 Cortex-A35 cores */ 39 A35_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a35"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 next-level-cache = <&A35_L2>; 45 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 46 #cooling-cells = <2>; 47 operating-points-v2 = <&a35_opp_table>; 48 }; 49 50 A35_1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a35"; 53 reg = <0x0 0x1>; 54 enable-method = "psci"; 55 next-level-cache = <&A35_L2>; 56 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 57 #cooling-cells = <2>; 58 operating-points-v2 = <&a35_opp_table>; 59 }; 60 61 A35_L2: l2-cache0 { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 }; 66 }; 67 68 a35_opp_table: opp-table { 69 compatible = "operating-points-v2"; 70 opp-shared; 71 72 opp-900000000 { 73 opp-hz = /bits/ 64 <900000000>; 74 opp-microvolt = <1000000>; 75 clock-latency-ns = <150000>; 76 }; 77 78 opp-1200000000 { 79 opp-hz = /bits/ 64 <1200000000>; 80 opp-microvolt = <1100000>; 81 clock-latency-ns = <150000>; 82 opp-suspend; 83 }; 84 }; 85 86 gic: interrupt-controller@51a00000 { 87 compatible = "arm,gic-v3"; 88 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 89 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 90 #interrupt-cells = <3>; 91 interrupt-controller; 92 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 93 }; 94 95 reserved-memory { 96 #address-cells = <2>; 97 #size-cells = <2>; 98 ranges; 99 100 dsp_reserved: dsp@92400000 { 101 reg = <0 0x92400000 0 0x2000000>; 102 no-map; 103 }; 104 }; 105 106 pmu { 107 compatible = "arm,armv8-pmuv3"; 108 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0"; 113 method = "smc"; 114 }; 115 116 system-controller { 117 compatible = "fsl,imx-scu"; 118 mbox-names = "tx0", 119 "rx0", 120 "gip3"; 121 mboxes = <&lsio_mu1 0 0 122 &lsio_mu1 1 0 123 &lsio_mu1 3 3>; 124 125 pd: power-controller { 126 compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd"; 127 #power-domain-cells = <1>; 128 }; 129 130 clk: clock-controller { 131 compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; 132 #clock-cells = <2>; 133 }; 134 135 scu_gpio: gpio { 136 compatible = "fsl,imx8qxp-sc-gpio"; 137 gpio-controller; 138 #gpio-cells = <2>; 139 }; 140 141 iomuxc: pinctrl { 142 compatible = "fsl,imx8dxl-iomuxc"; 143 }; 144 145 ocotp: ocotp { 146 compatible = "fsl,imx8qxp-scu-ocotp"; 147 #address-cells = <1>; 148 #size-cells = <1>; 149 150 fec_mac0: mac@2c4 { 151 reg = <0x2c4 6>; 152 }; 153 154 fec_mac1: mac@2c6 { 155 reg = <0x2c6 6>; 156 }; 157 }; 158 159 rtc: rtc { 160 compatible = "fsl,imx8qxp-sc-rtc"; 161 }; 162 163 sc_pwrkey: keys { 164 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 165 linux,keycodes = <KEY_POWER>; 166 wakeup-source; 167 }; 168 169 watchdog { 170 compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt"; 171 timeout-sec = <60>; 172 }; 173 174 tsens: thermal-sensor { 175 compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal"; 176 #thermal-sensor-cells = <1>; 177 }; 178 }; 179 180 timer { 181 compatible = "arm,armv8-timer"; 182 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 183 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 184 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 185 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 186 }; 187 188 thermal_zones: thermal-zones { 189 cpu-thermal { 190 polling-delay-passive = <250>; 191 polling-delay = <2000>; 192 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 193 194 trips { 195 cpu_alert0: trip0 { 196 temperature = <107000>; 197 hysteresis = <2000>; 198 type = "passive"; 199 }; 200 cpu_crit0: trip1 { 201 temperature = <127000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&cpu_alert0>; 210 cooling-device = 211 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 212 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 213 }; 214 }; 215 }; 216 }; 217 218 /* The two values below cannot be changed by the board */ 219 xtal32k: clock-xtal32k { 220 compatible = "fixed-clock"; 221 #clock-cells = <0>; 222 clock-frequency = <32768>; 223 clock-output-names = "xtal_32KHz"; 224 }; 225 226 xtal24m: clock-xtal24m { 227 compatible = "fixed-clock"; 228 #clock-cells = <0>; 229 clock-frequency = <24000000>; 230 clock-output-names = "xtal_24MHz"; 231 }; 232 233 /* sorted in register address */ 234 #include "imx8-ss-adma.dtsi" 235 #include "imx8-ss-conn.dtsi" 236 #include "imx8-ss-ddr.dtsi" 237 #include "imx8-ss-lsio.dtsi" 238}; 239 240#include "imx8dxl-ss-adma.dtsi" 241#include "imx8dxl-ss-conn.dtsi" 242#include "imx8dxl-ss-lsio.dtsi" 243#include "imx8dxl-ss-ddr.dtsi" 244