1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx8-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/clock/imx8-lpcg.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/pinctrl/pads-imx8dxl.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 ethernet1 = &eqos; 24 gpio0 = &lsio_gpio0; 25 gpio1 = &lsio_gpio1; 26 gpio2 = &lsio_gpio2; 27 gpio3 = &lsio_gpio3; 28 gpio4 = &lsio_gpio4; 29 gpio5 = &lsio_gpio5; 30 gpio6 = &lsio_gpio6; 31 gpio7 = &lsio_gpio7; 32 mu1 = &lsio_mu1; 33 spi0 = &lpspi0; 34 spi1 = &lpspi1; 35 spi2 = &lpspi2; 36 spi3 = &lpspi3; 37 }; 38 39 cpus: cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 /* We have 1 clusters with 2 Cortex-A35 cores */ 44 A35_0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a35"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 next-level-cache = <&A35_L2>; 50 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 51 #cooling-cells = <2>; 52 operating-points-v2 = <&a35_opp_table>; 53 }; 54 55 A35_1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a35"; 58 reg = <0x0 0x1>; 59 enable-method = "psci"; 60 next-level-cache = <&A35_L2>; 61 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 62 #cooling-cells = <2>; 63 operating-points-v2 = <&a35_opp_table>; 64 }; 65 66 A35_L2: l2-cache0 { 67 compatible = "cache"; 68 cache-level = <2>; 69 cache-unified; 70 }; 71 }; 72 73 a35_opp_table: opp-table { 74 compatible = "operating-points-v2"; 75 opp-shared; 76 77 opp-900000000 { 78 opp-hz = /bits/ 64 <900000000>; 79 opp-microvolt = <1000000>; 80 clock-latency-ns = <150000>; 81 }; 82 83 opp-1200000000 { 84 opp-hz = /bits/ 64 <1200000000>; 85 opp-microvolt = <1100000>; 86 clock-latency-ns = <150000>; 87 opp-suspend; 88 }; 89 }; 90 91 gic: interrupt-controller@51a00000 { 92 compatible = "arm,gic-v3"; 93 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 94 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 95 #address-cells = <0>; 96 #interrupt-cells = <3>; 97 interrupt-controller; 98 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 99 }; 100 101 reserved-memory { 102 #address-cells = <2>; 103 #size-cells = <2>; 104 ranges; 105 106 dsp_reserved: dsp@92400000 { 107 reg = <0 0x92400000 0 0x2000000>; 108 no-map; 109 }; 110 }; 111 112 pmu { 113 compatible = "arm,cortex-a35-pmu"; 114 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 115 }; 116 117 psci { 118 compatible = "arm,psci-1.0"; 119 method = "smc"; 120 }; 121 122 system-controller { 123 compatible = "fsl,imx-scu"; 124 mbox-names = "tx0", 125 "rx0", 126 "gip3"; 127 mboxes = <&lsio_mu1 0 0 128 &lsio_mu1 1 0 129 &lsio_mu1 3 3>; 130 131 pd: power-controller { 132 compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd"; 133 #power-domain-cells = <1>; 134 }; 135 136 clk: clock-controller { 137 compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; 138 #clock-cells = <2>; 139 }; 140 141 scu_gpio: gpio { 142 compatible = "fsl,imx8qxp-sc-gpio"; 143 gpio-controller; 144 #gpio-cells = <2>; 145 }; 146 147 iomuxc: pinctrl { 148 compatible = "fsl,imx8dxl-iomuxc"; 149 }; 150 151 ocotp: ocotp { 152 compatible = "fsl,imx8qxp-scu-ocotp"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 156 fec_mac0: mac@2c4 { 157 reg = <0x2c4 6>; 158 }; 159 160 fec_mac1: mac@2c6 { 161 reg = <0x2c6 6>; 162 }; 163 }; 164 165 rtc: rtc { 166 compatible = "fsl,imx8qxp-sc-rtc"; 167 }; 168 169 sc_pwrkey: keys { 170 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 171 linux,keycodes = <KEY_POWER>; 172 wakeup-source; 173 }; 174 175 watchdog { 176 compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt"; 177 timeout-sec = <60>; 178 }; 179 180 tsens: thermal-sensor { 181 compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal"; 182 #thermal-sensor-cells = <1>; 183 }; 184 }; 185 186 timer { 187 compatible = "arm,armv8-timer"; 188 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 189 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 190 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 191 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 192 }; 193 194 thermal_zones: thermal-zones { 195 cpu-thermal { 196 polling-delay-passive = <250>; 197 polling-delay = <2000>; 198 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 199 200 trips { 201 cpu_alert0: trip0 { 202 temperature = <107000>; 203 hysteresis = <2000>; 204 type = "passive"; 205 }; 206 cpu_crit0: trip1 { 207 temperature = <127000>; 208 hysteresis = <2000>; 209 type = "critical"; 210 }; 211 }; 212 213 cooling-maps { 214 map0 { 215 trip = <&cpu_alert0>; 216 cooling-device = 217 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 218 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 219 }; 220 }; 221 }; 222 }; 223 224 /* The two values below cannot be changed by the board */ 225 xtal32k: clock-xtal32k { 226 compatible = "fixed-clock"; 227 #clock-cells = <0>; 228 clock-frequency = <32768>; 229 clock-output-names = "xtal_32KHz"; 230 }; 231 232 xtal24m: clock-xtal24m { 233 compatible = "fixed-clock"; 234 #clock-cells = <0>; 235 clock-frequency = <24000000>; 236 clock-output-names = "xtal_24MHz"; 237 }; 238 239 /* sorted in register address */ 240 #include "imx8-ss-cm40.dtsi" 241 #include "imx8-ss-adma.dtsi" 242 #include "imx8-ss-conn.dtsi" 243 #include "imx8-ss-ddr.dtsi" 244 #include "imx8-ss-lsio.dtsi" 245 #include "imx8-ss-hsio.dtsi" 246}; 247 248#include "imx8dxl-ss-adma.dtsi" 249#include "imx8dxl-ss-conn.dtsi" 250#include "imx8dxl-ss-lsio.dtsi" 251#include "imx8dxl-ss-ddr.dtsi" 252#include "imx8dxl-ss-hsio.dtsi" 253 254&cm40_intmux { 255 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 263}; 264