1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6#include <dt-bindings/clock/imx8-clock.h> 7#include <dt-bindings/firmware/imx/rsrc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/pinctrl/pads-imx8dxl.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 ethernet0 = &fec1; 21 ethernet1 = &eqos; 22 gpio0 = &lsio_gpio0; 23 gpio1 = &lsio_gpio1; 24 gpio2 = &lsio_gpio2; 25 gpio3 = &lsio_gpio3; 26 gpio4 = &lsio_gpio4; 27 gpio5 = &lsio_gpio5; 28 gpio6 = &lsio_gpio6; 29 gpio7 = &lsio_gpio7; 30 mu1 = &lsio_mu1; 31 }; 32 33 cpus: cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 /* We have 1 clusters with 2 Cortex-A35 cores */ 38 A35_0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a35"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 next-level-cache = <&A35_L2>; 44 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 45 #cooling-cells = <2>; 46 operating-points-v2 = <&a35_opp_table>; 47 }; 48 49 A35_1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a35"; 52 reg = <0x0 0x1>; 53 enable-method = "psci"; 54 next-level-cache = <&A35_L2>; 55 clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; 56 #cooling-cells = <2>; 57 operating-points-v2 = <&a35_opp_table>; 58 }; 59 60 A35_L2: l2-cache0 { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 }; 65 }; 66 67 a35_opp_table: opp-table { 68 compatible = "operating-points-v2"; 69 opp-shared; 70 71 opp-900000000 { 72 opp-hz = /bits/ 64 <900000000>; 73 opp-microvolt = <1000000>; 74 clock-latency-ns = <150000>; 75 }; 76 77 opp-1200000000 { 78 opp-hz = /bits/ 64 <1200000000>; 79 opp-microvolt = <1100000>; 80 clock-latency-ns = <150000>; 81 opp-suspend; 82 }; 83 }; 84 85 gic: interrupt-controller@51a00000 { 86 compatible = "arm,gic-v3"; 87 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 88 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 89 #interrupt-cells = <3>; 90 interrupt-controller; 91 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 92 }; 93 94 reserved-memory { 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges; 98 99 dsp_reserved: dsp@92400000 { 100 reg = <0 0x92400000 0 0x2000000>; 101 no-map; 102 }; 103 }; 104 105 pmu { 106 compatible = "arm,armv8-pmuv3"; 107 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 108 }; 109 110 psci { 111 compatible = "arm,psci-1.0"; 112 method = "smc"; 113 }; 114 115 system-controller { 116 compatible = "fsl,imx-scu"; 117 mbox-names = "tx0", 118 "rx0", 119 "gip3"; 120 mboxes = <&lsio_mu1 0 0 121 &lsio_mu1 1 0 122 &lsio_mu1 3 3>; 123 124 pd: power-controller { 125 compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd"; 126 #power-domain-cells = <1>; 127 }; 128 129 clk: clock-controller { 130 compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; 131 #clock-cells = <2>; 132 }; 133 134 scu_gpio: gpio { 135 compatible = "fsl,imx8qxp-sc-gpio"; 136 gpio-controller; 137 #gpio-cells = <2>; 138 }; 139 140 iomuxc: pinctrl { 141 compatible = "fsl,imx8dxl-iomuxc"; 142 }; 143 144 ocotp: ocotp { 145 compatible = "fsl,imx8qxp-scu-ocotp"; 146 #address-cells = <1>; 147 #size-cells = <1>; 148 149 fec_mac0: mac@2c4 { 150 reg = <0x2c4 6>; 151 }; 152 153 fec_mac1: mac@2c6 { 154 reg = <0x2c6 6>; 155 }; 156 }; 157 158 rtc: rtc { 159 compatible = "fsl,imx8qxp-sc-rtc"; 160 }; 161 162 sc_pwrkey: keys { 163 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 164 linux,keycodes = <KEY_POWER>; 165 wakeup-source; 166 }; 167 168 watchdog { 169 compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt"; 170 timeout-sec = <60>; 171 }; 172 173 tsens: thermal-sensor { 174 compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal"; 175 #thermal-sensor-cells = <1>; 176 }; 177 }; 178 179 timer { 180 compatible = "arm,armv8-timer"; 181 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 182 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 183 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 184 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 185 }; 186 187 thermal_zones: thermal-zones { 188 cpu-thermal { 189 polling-delay-passive = <250>; 190 polling-delay = <2000>; 191 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 192 193 trips { 194 cpu_alert0: trip0 { 195 temperature = <107000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 cpu_crit0: trip1 { 200 temperature = <127000>; 201 hysteresis = <2000>; 202 type = "critical"; 203 }; 204 }; 205 206 cooling-maps { 207 map0 { 208 trip = <&cpu_alert0>; 209 cooling-device = 210 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 212 }; 213 }; 214 }; 215 }; 216 217 /* The two values below cannot be changed by the board */ 218 xtal32k: clock-xtal32k { 219 compatible = "fixed-clock"; 220 #clock-cells = <0>; 221 clock-frequency = <32768>; 222 clock-output-names = "xtal_32KHz"; 223 }; 224 225 xtal24m: clock-xtal24m { 226 compatible = "fixed-clock"; 227 #clock-cells = <0>; 228 clock-frequency = <24000000>; 229 clock-output-names = "xtal_24MHz"; 230 }; 231 232 /* sorted in register address */ 233 #include "imx8-ss-adma.dtsi" 234 #include "imx8-ss-conn.dtsi" 235 #include "imx8-ss-ddr.dtsi" 236 #include "imx8-ss-lsio.dtsi" 237}; 238 239#include "imx8dxl-ss-adma.dtsi" 240#include "imx8dxl-ss-conn.dtsi" 241#include "imx8dxl-ss-lsio.dtsi" 242#include "imx8dxl-ss-ddr.dtsi" 243