1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6&flexspi0 { 7 compatible = "nxp,imx8dxl-fspi"; 8 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 9}; 10 11&lsio_gpio0 { 12 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; 13 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 14 gpio-ranges = <&iomuxc 0 47 13>, 15 <&iomuxc 13 61 4>, 16 <&iomuxc 19 67 4>, 17 <&iomuxc 24 72 1>; 18}; 19 20&lsio_gpio1 { 21 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; 22 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 23 gpio-ranges = <&iomuxc 4 74 5>, 24 <&iomuxc 9 80 16>; 25}; 26 27&lsio_gpio2 { 28 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; 29 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 30 gpio-ranges = <&iomuxc 1 98 2>, 31 <&iomuxc 3 101 1>, 32 <&iomuxc 5 107 8>; 33}; 34 35&lsio_gpio3 { 36 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; 37 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 38 gpio-ranges = <&iomuxc 0 115 4>, 39 <&iomuxc 9 121 1>, 40 <&iomuxc 10 120 1>, 41 <&iomuxc 11 123 1>, 42 <&iomuxc 12 122 1>, 43 <&iomuxc 13 125 1>, 44 <&iomuxc 14 124 1>, 45 <&iomuxc 16 126 1>, 46 <&iomuxc 17 128 1>, 47 <&iomuxc 18 131 1>, 48 <&iomuxc 19 130 1>, 49 <&iomuxc 20 133 1>, 50 <&iomuxc 21 132 1>, 51 <&iomuxc 22 129 1>, 52 <&iomuxc 23 134 1>; 53}; 54 55&lsio_gpio4 { 56 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; 57 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 58 gpio-ranges = <&iomuxc 0 0 3>, 59 <&iomuxc 3 4 4>, 60 <&iomuxc 7 9 12>, 61 <&iomuxc 19 22 2>, 62 <&iomuxc 21 25 2>, 63 <&iomuxc 29 29 3>; 64}; 65 66&lsio_gpio5 { 67 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; 68 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 69 gpio-ranges = <&iomuxc 0 32 3>, 70 <&iomuxc 3 36 6>, 71 <&iomuxc 9 43 3>; 72}; 73 74&lsio_gpio6 { 75 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; 76 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 77 gpio-ranges = <&iomuxc 0 53 7>, 78 <&iomuxc 8 86 10>, 79 <&iomuxc 19 107 8>; 80}; 81 82&lsio_gpio7 { 83 compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; 84 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 85 gpio-ranges = <&iomuxc 0 0 3>, 86 <&iomuxc 3 4 4>, 87 <&iomuxc 8 22 2>, 88 <&iomuxc 10 25 2>, 89 <&iomuxc 16 44 2>; 90}; 91 92&lsio_mu0 { 93 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 94 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 95}; 96 97&lsio_mu1 { 98 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 99 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 100}; 101 102&lsio_mu2 { 103 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 104 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 105}; 106 107&lsio_mu3 { 108 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 109 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 110}; 111 112&lsio_mu4 { 113 compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 114 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 115}; 116 117&lsio_mu5 { 118 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 119 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 120}; 121