1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6/delete-node/ &enet1_lpcg; 7/delete-node/ &fec2; 8/delete-node/ &usbotg3; 9/delete-node/ &usb3_phy; 10 11/ { 12 conn_enet0_root_clk: clock-conn-enet0-root { 13 compatible = "fixed-clock"; 14 #clock-cells = <0>; 15 clock-frequency = <250000000>; 16 clock-output-names = "conn_enet0_root_clk"; 17 }; 18 19 clk_dummy: clock-dummy { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <0>; 23 clock-output-names = "clk_dummy"; 24 }; 25}; 26 27&conn_subsys { 28 eqos: ethernet@5b050000 { 29 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; 30 reg = <0x5b050000 0x10000>; 31 interrupt-parent = <&gic>; 32 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 34 interrupt-names = "macirq", "eth_wake_irq"; 35 clocks = <&eqos_lpcg IMX_LPCG_CLK_4>, 36 <&eqos_lpcg IMX_LPCG_CLK_6>, 37 <&eqos_lpcg IMX_LPCG_CLK_0>, 38 <&eqos_lpcg IMX_LPCG_CLK_5>, 39 <&eqos_lpcg IMX_LPCG_CLK_2>; 40 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; 41 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; 42 assigned-clock-rates = <125000000>; 43 power-domains = <&pd IMX_SC_R_ENET_1>; 44 status = "disabled"; 45 }; 46 47 usbotg2: usb@5b0e0000 { 48 compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb"; 49 reg = <0x5b0e0000 0x200>; 50 interrupt-parent = <&gic>; 51 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 52 fsl,usbphy = <&usbphy2>; 53 fsl,usbmisc = <&usbmisc2 0>; 54 /* 55 * usbotg1 and usbotg2 share one clcok. 56 * scu firmware disables the access to the clock and keeps 57 * it always on in case other core (M4) uses one of these. 58 */ 59 clocks = <&clk_dummy>; 60 ahb-burst-config = <0x0>; 61 tx-burst-size-dword = <0x10>; 62 rx-burst-size-dword = <0x10>; 63 power-domains = <&pd IMX_SC_R_USB_1>; 64 status = "disabled"; 65 }; 66 67 usbmisc2: usbmisc@5b0e0200 { 68 #index-cells = <1>; 69 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 70 reg = <0x5b0e0200 0x200>; 71 }; 72 73 usbphy2: usbphy@5b110000 { 74 compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; 75 reg = <0x5b110000 0x1000>; 76 clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>; 77 power-domains = <&pd IMX_SC_R_USB_1_PHY>; 78 status = "disabled"; 79 }; 80 81 eqos_lpcg: clock-controller@5b240000 { 82 compatible = "fsl,imx8qxp-lpcg"; 83 reg = <0x5b240000 0x10000>; 84 #clock-cells = <1>; 85 clocks = <&conn_enet0_root_clk>, 86 <&conn_axi_clk>, 87 <&conn_axi_clk>, 88 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 89 <&conn_ipg_clk>; 90 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>, 91 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 92 <IMX_LPCG_CLK_6>; 93 clock-output-names = "eqos_ptp", 94 "eqos_mem_clk", 95 "eqos_aclk", 96 "eqos_clk", 97 "eqos_csr_clk"; 98 power-domains = <&pd IMX_SC_R_ENET_1>; 99 }; 100 101 usb2_2_lpcg: clock-controller@5b280000 { 102 compatible = "fsl,imx8qxp-lpcg"; 103 reg = <0x5b280000 0x10000>; 104 #clock-cells = <1>; 105 clock-indices = <IMX_LPCG_CLK_7>; 106 clocks = <&conn_ipg_clk>; 107 clock-output-names = "usboh3_2_phy_ipg_clk"; 108 power-domains = <&pd IMX_SC_R_USB_1_PHY>; 109 }; 110 111}; 112 113&dma_apbh { 114 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 118}; 119 120&enet0_lpcg { 121 clocks = <&conn_enet0_root_clk>, 122 <&conn_enet0_root_clk>, 123 <&conn_axi_clk>, 124 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, 125 <&conn_ipg_clk>, 126 <&conn_ipg_clk>; 127}; 128 129&fec1 { 130 compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec"; 131 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 135 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; 136 assigned-clock-rates = <125000000>; 137}; 138 139&gpmi { 140 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 141}; 142 143&usbphy1 { 144 compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; 145}; 146 147&usdhc1 { 148 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; 149 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 150}; 151 152&usdhc2 { 153 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; 154 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 155}; 156 157&usdhc3 { 158 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; 159 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 160}; 161 162&usbotg1 { 163 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 164 /* 165 * usbotg1 and usbotg2 share one clock 166 * scfw disable clock access and keep it always on 167 * in case other core (M4) use one of these. 168 */ 169 clocks = <&clk_dummy>; 170}; 171