1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6/delete-node/ &enet1_lpcg; 7/delete-node/ &fec2; 8 9&conn_subsys { 10 conn_enet0_root_clk: clock-conn-enet0-root { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <250000000>; 14 clock-output-names = "conn_enet0_root_clk"; 15 }; 16 17 eqos: ethernet@5b050000 { 18 compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; 19 reg = <0x5b050000 0x10000>; 20 interrupt-parent = <&gic>; 21 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 22 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 23 interrupt-names = "eth_wake_irq", "macirq"; 24 clocks = <&eqos_lpcg IMX_LPCG_CLK_4>, 25 <&eqos_lpcg IMX_LPCG_CLK_6>, 26 <&eqos_lpcg IMX_LPCG_CLK_0>, 27 <&eqos_lpcg IMX_LPCG_CLK_5>, 28 <&eqos_lpcg IMX_LPCG_CLK_2>; 29 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; 30 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; 31 assigned-clock-rates = <125000000>; 32 power-domains = <&pd IMX_SC_R_ENET_1>; 33 status = "disabled"; 34 }; 35 36 usbotg2: usb@5b0e0000 { 37 compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb"; 38 reg = <0x5b0e0000 0x200>; 39 interrupt-parent = <&gic>; 40 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 41 fsl,usbphy = <&usbphy2>; 42 fsl,usbmisc = <&usbmisc2 0>; 43 /* 44 * usbotg1 and usbotg2 share one clcok. 45 * scu firmware disables the access to the clock and keeps 46 * it always on in case other core (M4) uses one of these. 47 */ 48 clocks = <&clk_dummy>; 49 ahb-burst-config = <0x0>; 50 tx-burst-size-dword = <0x10>; 51 rx-burst-size-dword = <0x10>; 52 #stream-id-cells = <1>; 53 power-domains = <&pd IMX_SC_R_USB_1>; 54 status = "disabled"; 55 56 clk_dummy: clock-dummy { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <0>; 60 clock-output-names = "clk_dummy"; 61 }; 62 }; 63 64 usbmisc2: usbmisc@5b0e0200 { 65 #index-cells = <1>; 66 compatible = "fsl,imx7ulp-usbmisc"; 67 reg = <0x5b0e0200 0x200>; 68 }; 69 70 usbphy2: usbphy@0x5b110000 { 71 compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; 72 reg = <0x5b110000 0x1000>; 73 clocks = <&usb2_2_lpcg IMX_LPCG_CLK_7>; 74 power-domains = <&pd IMX_SC_R_USB_1_PHY>; 75 status = "disabled"; 76 }; 77 78 eqos_lpcg: clock-controller@5b240000 { 79 compatible = "fsl,imx8qxp-lpcg"; 80 reg = <0x5b240000 0x10000>; 81 #clock-cells = <1>; 82 clocks = <&conn_enet0_root_clk>, 83 <&conn_axi_clk>, 84 <&conn_axi_clk>, 85 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 86 <&conn_ipg_clk>; 87 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>, 88 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 89 <IMX_LPCG_CLK_6>; 90 clock-output-names = "eqos_ptp", 91 "eqos_mem_clk", 92 "eqos_aclk", 93 "eqos_clk", 94 "eqos_csr_clk"; 95 power-domains = <&pd IMX_SC_R_ENET_1>; 96 }; 97 98 usb2_2_lpcg: clock-controller@5b280000 { 99 compatible = "fsl,imx8qxp-lpcg"; 100 reg = <0x5b280000 0x10000>; 101 #clock-cells = <1>; 102 clock-indices = <IMX_LPCG_CLK_7>; 103 clocks = <&conn_ipg_clk>; 104 clock-output-names = "usboh3_2_phy_ipg_clk"; 105 power-domains = <&pd IMX_SC_R_USB_1_PHY>; 106 }; 107 108}; 109 110&enet0_lpcg { 111 clocks = <&conn_enet0_root_clk>, 112 <&conn_enet0_root_clk>, 113 <&conn_axi_clk>, 114 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, 115 <&conn_ipg_clk>, 116 <&conn_ipg_clk>; 117}; 118 119&fec1 { 120 compatible = "fsl,imx8qm-fec"; 121 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 125 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; 126 assigned-clock-rates = <125000000>; 127}; 128 129&usdhc1 { 130 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; 131 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 132}; 133 134&usdhc2 { 135 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; 136 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 137}; 138 139&usdhc3 { 140 compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; 141 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 142}; 143 144&usbotg1 { 145 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 146 /* 147 * usbotg1 and usbotg2 share one clock 148 * scfw disable clock access and keep it always on 149 * in case other core (M4) use one of these. 150 */ 151 clocks = <&clk_dummy>; 152}; 153