1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6&audio_ipg_clk { 7 clock-frequency = <160000000>; 8}; 9 10&dma_ipg_clk { 11 clock-frequency = <160000000>; 12}; 13 14&adc0 { 15 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 16}; 17 18&edma0 { 19 reg = <0x591f0000 0x1a0000>; 20 #dma-cells = <3>; 21 dma-channels = <25>; 22 dma-channel-mask = <0x1c0cc0>; 23 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ 24 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 25 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 26 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 27 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 28 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 29 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 30 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 31 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ 32 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ 36 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ 38 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ 40 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ 41 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */ 45 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */ 46 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */ 47 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */ 48 power-domains = <&pd IMX_SC_R_DMA_0_CH0>, 49 <&pd IMX_SC_R_DMA_0_CH1>, 50 <&pd IMX_SC_R_DMA_0_CH2>, 51 <&pd IMX_SC_R_DMA_0_CH3>, 52 <&pd IMX_SC_R_DMA_0_CH4>, 53 <&pd IMX_SC_R_DMA_0_CH5>, 54 <&pd IMX_SC_R_DMA_0_CH6>, 55 <&pd IMX_SC_R_DMA_0_CH7>, 56 <&pd IMX_SC_R_DMA_0_CH8>, 57 <&pd IMX_SC_R_DMA_0_CH9>, 58 <&pd IMX_SC_R_DMA_0_CH10>, 59 <&pd IMX_SC_R_DMA_0_CH11>, 60 <&pd IMX_SC_R_DMA_0_CH12>, 61 <&pd IMX_SC_R_DMA_0_CH13>, 62 <&pd IMX_SC_R_DMA_0_CH14>, 63 <&pd IMX_SC_R_DMA_0_CH15>, 64 <&pd IMX_SC_R_DMA_0_CH16>, 65 <&pd IMX_SC_R_DMA_0_CH17>, 66 <&pd IMX_SC_R_DMA_0_CH18>, 67 <&pd IMX_SC_R_DMA_0_CH19>, 68 <&pd IMX_SC_R_DMA_0_CH20>, 69 <&pd IMX_SC_R_DMA_0_CH21>, 70 <&pd IMX_SC_R_DMA_0_CH22>, 71 <&pd IMX_SC_R_DMA_0_CH23>, 72 <&pd IMX_SC_R_DMA_0_CH24>; 73}; 74 75&edma2 { 76 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 92}; 93 94&edma3 { 95 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; 103}; 104 105&flexcan1 { 106 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 107}; 108 109&flexcan2 { 110 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 111}; 112 113&flexcan3 { 114 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 115}; 116 117&i2c0 { 118 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; 119 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 120 dma-names = "tx","rx"; 121 dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>; 122}; 123 124&i2c1 { 125 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; 126 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 127 dma-names = "tx","rx"; 128 dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>; 129}; 130 131&i2c2 { 132 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; 133 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 134 dma-names = "tx","rx"; 135 dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>; 136}; 137 138&i2c3 { 139 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; 140 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 141 dma-names = "tx","rx"; 142 dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>; 143}; 144 145&lpuart0 { 146 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; 147 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 148}; 149 150&lpuart1 { 151 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; 152 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 153}; 154 155&lpuart2 { 156 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; 157 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 158}; 159 160&lpuart3 { 161 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; 162 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 163}; 164 165&lpspi0 { 166 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 167}; 168 169&lpspi1 { 170 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 171}; 172 173&lpspi2 { 174 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 175}; 176 177&lpspi3 { 178 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 179}; 180