1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8dxl.dtsi" 9 10/ { 11 model = "Freescale i.MX8DXL EVK"; 12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl"; 13 14 aliases { 15 i2c2 = &i2c2; 16 mmc0 = &usdhc1; 17 mmc1 = &usdhc2; 18 serial0 = &lpuart0; 19 }; 20 21 chosen { 22 stdout-path = &lpuart0; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 reg = <0x00000000 0x80000000 0 0x40000000>; 28 }; 29 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 /* 36 * Memory reserved for optee usage. Please do not use. 37 * This will be automatically added to dtb if OP-TEE is installed. 38 * optee@96000000 { 39 * reg = <0 0x96000000 0 0x2000000>; 40 * no-map; 41 * }; 42 */ 43 44 /* global autoconfigured region for contiguous allocations */ 45 linux,cma { 46 compatible = "shared-dma-pool"; 47 reusable; 48 size = <0 0x14000000>; 49 alloc-ranges = <0 0x98000000 0 0x14000000>; 50 linux,cma-default; 51 }; 52 }; 53 54 mux3_en: regulator-0 { 55 compatible = "regulator-fixed"; 56 regulator-min-microvolt = <3300000>; 57 regulator-max-microvolt = <3300000>; 58 regulator-name = "mux3_en"; 59 gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>; 60 regulator-always-on; 61 }; 62 63 reg_fec1_sel: regulator-1 { 64 compatible = "regulator-fixed"; 65 regulator-name = "fec1_supply"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>; 69 regulator-always-on; 70 status = "disabled"; 71 }; 72 73 reg_fec1_io: regulator-2 { 74 compatible = "regulator-fixed"; 75 regulator-name = "fec1_io_supply"; 76 regulator-min-microvolt = <1800000>; 77 regulator-max-microvolt = <1800000>; 78 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; 79 enable-active-high; 80 regulator-always-on; 81 status = "disabled"; 82 }; 83 84 reg_can0_stby: regulator-4 { 85 compatible = "regulator-fixed"; 86 regulator-name = "can0-stby"; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>; 90 enable-active-high; 91 }; 92 93 reg_can1_stby: regulator-5 { 94 compatible = "regulator-fixed"; 95 regulator-name = "can1-stby"; 96 regulator-min-microvolt = <3300000>; 97 regulator-max-microvolt = <3300000>; 98 gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>; 99 enable-active-high; 100 }; 101 102 reg_usdhc2_vmmc: regulator-3 { 103 compatible = "regulator-fixed"; 104 regulator-name = "SD1_SPWR"; 105 regulator-min-microvolt = <3000000>; 106 regulator-max-microvolt = <3000000>; 107 gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>; 108 enable-active-high; 109 off-on-delay-us = <3480>; 110 }; 111 112 reg_vref_1v8: regulator-adc-vref { 113 compatible = "regulator-fixed"; 114 regulator-name = "vref_1v8"; 115 regulator-min-microvolt = <1800000>; 116 regulator-max-microvolt = <1800000>; 117 }; 118 119 mii_select: regulator-4 { 120 compatible = "regulator-fixed"; 121 regulator-name = "mii-select"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>; 125 enable-active-high; 126 regulator-always-on; 127 }; 128}; 129 130&adc0 { 131 vref-supply = <®_vref_1v8>; 132 status = "okay"; 133}; 134 135&eqos { 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_eqos>; 138 phy-mode = "rgmii-id"; 139 phy-handle = <ðphy0>; 140 nvmem-cells = <&fec_mac1>; 141 nvmem-cell-names = "mac-address"; 142 status = "okay"; 143 144 mdio { 145 compatible = "snps,dwmac-mdio"; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 149 ethphy0: ethernet-phy@0 { 150 compatible = "ethernet-phy-ieee802.3-c22"; 151 reg = <0>; 152 eee-broken-1000t; 153 qca,disable-smarteee; 154 qca,disable-hibernation-mode; 155 reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; 156 reset-assert-us = <20>; 157 reset-deassert-us = <200000>; 158 vddio-supply = <&vddio0>; 159 160 vddio0: vddio-regulator { 161 regulator-min-microvolt = <1800000>; 162 regulator-max-microvolt = <1800000>; 163 }; 164 }; 165 }; 166}; 167 168/* 169 * fec1 shares the some PINs with usdhc2. 170 * by default usdhc2 is enabled in this dts. 171 * Please disable usdhc2 to enable fec1 172 */ 173&fec1 { 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_fec1>; 176 phy-mode = "rgmii-txid"; 177 phy-handle = <ðphy1>; 178 fsl,magic-packet; 179 rx-internal-delay-ps = <2000>; 180 nvmem-cells = <&fec_mac0>; 181 nvmem-cell-names = "mac-address"; 182 status = "disabled"; 183 184 mdio { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 ethphy1: ethernet-phy@1 { 189 compatible = "ethernet-phy-ieee802.3-c22"; 190 reg = <1>; 191 reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>; 192 reset-assert-us = <10000>; 193 qca,disable-smarteee; 194 vddio-supply = <&vddio1>; 195 196 vddio1: vddio-regulator { 197 regulator-min-microvolt = <1800000>; 198 regulator-max-microvolt = <1800000>; 199 }; 200 }; 201 }; 202}; 203 204&flexspi0 { 205 pinctrl-names = "default"; 206 pinctrl-0 = <&pinctrl_flexspi0>; 207 status = "okay"; 208 209 mt35xu512aba0: flash@0 { 210 reg = <0>; 211 #address-cells = <1>; 212 #size-cells = <1>; 213 compatible = "jedec,spi-nor"; 214 spi-max-frequency = <133000000>; 215 spi-tx-bus-width = <8>; 216 spi-rx-bus-width = <8>; 217 }; 218}; 219 220&i2c2 { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 clock-frequency = <100000>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_i2c2>; 226 status = "okay"; 227 228 pca6416_1: gpio@20 { 229 compatible = "ti,tca6416"; 230 reg = <0x20>; 231 gpio-controller; 232 #gpio-cells = <2>; 233 }; 234 235 pca6416_2: gpio@21 { 236 compatible = "ti,tca6416"; 237 reg = <0x21>; 238 gpio-controller; 239 #gpio-cells = <2>; 240 }; 241 242 pca9548_1: i2c-mux@70 { 243 compatible = "nxp,pca9548"; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 reg = <0x70>; 247 248 i2c@0 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 reg = <0x0>; 252 253 max7322: gpio@68 { 254 compatible = "maxim,max7322"; 255 reg = <0x68>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 status = "disabled"; 259 }; 260 }; 261 262 i2c@4 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 reg = <0x4>; 266 }; 267 268 i2c@5 { 269 #address-cells = <1>; 270 #size-cells = <0>; 271 reg = <0x5>; 272 }; 273 274 i2c@6 { 275 #address-cells = <1>; 276 #size-cells = <0>; 277 reg = <0x6>; 278 }; 279 }; 280}; 281 282&i2c3 { 283 #address-cells = <1>; 284 #size-cells = <0>; 285 clock-frequency = <100000>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_i2c3>; 288 status = "okay"; 289 290 pca6416_3: gpio@20 { 291 compatible = "ti,tca6416"; 292 reg = <0x20>; 293 gpio-controller; 294 #gpio-cells = <2>; 295 interrupt-parent = <&lsio_gpio2>; 296 interrupts = <5 IRQ_TYPE_EDGE_RISING>; 297 }; 298 299 pca9548_2: i2c-mux@70 { 300 compatible = "nxp,pca9548"; 301 reg = <0x70>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 i2c@0 { 306 #address-cells = <1>; 307 #size-cells = <0>; 308 reg = <0x0>; 309 }; 310 311 i2c@1 { 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x1>; 315 }; 316 317 i2c@2 { 318 #address-cells = <1>; 319 #size-cells = <0>; 320 reg = <0x2>; 321 }; 322 323 i2c@3 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 reg = <0x3>; 327 }; 328 329 i2c@4 { 330 #address-cells = <1>; 331 #size-cells = <0>; 332 reg = <0x4>; 333 }; 334 }; 335}; 336 337&lpuart0 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_lpuart0>; 340 status = "okay"; 341}; 342 343&flexcan2 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_flexcan2>; 346 xceiver-supply = <®_can0_stby>; 347 status = "okay"; 348}; 349 350&flexcan3 { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_flexcan3>; 353 xceiver-supply = <®_can1_stby>; 354 status = "okay"; 355}; 356 357&lsio_gpio4 { 358 status = "okay"; 359}; 360 361&lsio_gpio5 { 362 status = "okay"; 363}; 364 365&thermal_zones { 366 pmic-thermal { 367 polling-delay-passive = <250>; 368 polling-delay = <2000>; 369 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; 370 371 trips { 372 pmic_alert0: trip0 { 373 temperature = <110000>; 374 hysteresis = <2000>; 375 type = "passive"; 376 }; 377 378 pmic_crit0: trip1 { 379 temperature = <125000>; 380 hysteresis = <2000>; 381 type = "critical"; 382 }; 383 }; 384 385 cooling-maps { 386 map0 { 387 trip = <&pmic_alert0>; 388 cooling-device = 389 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 390 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 391 }; 392 }; 393 }; 394}; 395 396&usbphy1 { 397 /* USB eye diagram tests result */ 398 fsl,tx-d-cal = <114>; 399 status = "okay"; 400}; 401 402&usbotg1 { 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_usbotg1>; 405 srp-disable; 406 hnp-disable; 407 adp-disable; 408 power-active-high; 409 disable-over-current; 410 status = "okay"; 411}; 412 413&usbphy2 { 414 /* USB eye diagram tests result */ 415 fsl,tx-d-cal = <111>; 416 status = "okay"; 417}; 418 419&usbotg2 { 420 pinctrl-names = "default"; 421 pinctrl-0 = <&pinctrl_usbotg2>; 422 srp-disable; 423 hnp-disable; 424 adp-disable; 425 power-active-high; 426 disable-over-current; 427 status = "okay"; 428}; 429 430&usdhc1 { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_usdhc1>; 433 bus-width = <8>; 434 no-sd; 435 no-sdio; 436 non-removable; 437 status = "okay"; 438}; 439 440&usdhc2 { 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 443 bus-width = <4>; 444 vmmc-supply = <®_usdhc2_vmmc>; 445 cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>; 446 wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; 447 status = "okay"; 448}; 449 450&lpspi3 { 451 fsl,spi-only-use-cs1-sel; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pinctrl_lpspi3>; 454 status = "okay"; 455 456 spidev0: spi@0 { 457 reg = <0>; 458 compatible = "rohm,dh2228fv"; 459 spi-max-frequency = <30000000>; 460 }; 461}; 462 463&iomuxc { 464 pinctrl-names = "default"; 465 pinctrl-0 = <&pinctrl_hog>; 466 467 pinctrl_hog: hoggrp { 468 fsl,pins = < 469 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 470 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0 471 IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c 472 IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c 473 >; 474 }; 475 476 pinctrl_usbotg1: usbotg1grp { 477 fsl,pins = < 478 IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 479 >; 480 }; 481 482 pinctrl_usbotg2: usbotg2grp { 483 fsl,pins = < 484 IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021 485 >; 486 }; 487 488 pinctrl_eqos: eqosgrp { 489 fsl,pins = < 490 IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020 491 IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 492 IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020 493 IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020 494 IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020 495 IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020 496 IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020 497 IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020 498 IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020 499 IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020 500 IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020 501 IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020 502 IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020 503 IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020 504 >; 505 }; 506 507 pinctrl_flexspi0: flexspi0grp { 508 fsl,pins = < 509 IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 510 IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 511 IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 512 IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 513 IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 514 IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 515 IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 516 IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 517 IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 518 IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 519 IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 520 IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 521 IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 522 IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 523 >; 524 }; 525 526 pinctrl_flexcan2: flexcan2grp { 527 fsl,pins = < 528 IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021 529 IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021 530 >; 531 }; 532 533 pinctrl_flexcan3: flexcan3grp { 534 fsl,pins = < 535 IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021 536 IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021 537 >; 538 }; 539 540 pinctrl_fec1: fec1grp { 541 fsl,pins = < 542 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 543 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 544 IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020 545 IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 546 IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 547 IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 548 IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 549 IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 550 IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 551 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 552 IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 553 IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 554 IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 555 IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 556 IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 557 IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 558 >; 559 }; 560 561 pinctrl_lpspi3: lpspi3grp { 562 fsl,pins = < 563 IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040 564 IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040 565 IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040 566 IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040 567 >; 568 }; 569 570 pinctrl_i2c2: i2c2grp { 571 fsl,pins = < 572 IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 573 IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 574 >; 575 }; 576 577 pinctrl_cm40_lpuart: cm40lpuartgrp { 578 fsl,pins = < 579 IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020 580 IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020 581 >; 582 }; 583 584 pinctrl_i2c3: i2c3grp { 585 fsl,pins = < 586 IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 587 IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 588 >; 589 }; 590 591 pinctrl_lpuart0: lpuart0grp { 592 fsl,pins = < 593 IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020 594 IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020 595 >; 596 }; 597 598 pinctrl_usdhc1: usdhc1grp { 599 fsl,pins = < 600 IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 601 IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 602 IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 603 IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 604 IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 605 IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 606 IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 607 IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 608 IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 609 IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 610 IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 611 >; 612 }; 613 614 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 615 fsl,pins = < 616 IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */ 617 IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ 618 IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ 619 >; 620 }; 621 622 pinctrl_usdhc2: usdhc2grp { 623 fsl,pins = < 624 IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 625 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 626 IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 627 IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 628 IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 629 IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 630 IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 631 >; 632 }; 633}; 634