1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2020 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10lsio_subsys: bus@5d000000 { 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, 15 <0x08000000 0x0 0x08000000 0x10000000>; 16 17 lsio_mem_clk: clock-lsio-mem { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <200000000>; 21 clock-output-names = "lsio_mem_clk"; 22 }; 23 24 lsio_bus_clk: clock-lsio-bus { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <100000000>; 28 clock-output-names = "lsio_bus_clk"; 29 }; 30 31 lsio_pwm0: pwm@5d000000 { 32 compatible = "fsl,imx27-pwm"; 33 reg = <0x5d000000 0x10000>; 34 clock-names = "ipg", "per"; 35 clocks = <&pwm0_lpcg 4>, 36 <&pwm0_lpcg 1>; 37 assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; 38 assigned-clock-rates = <24000000>; 39 #pwm-cells = <2>; 40 status = "disabled"; 41 }; 42 43 lsio_pwm1: pwm@5d010000 { 44 compatible = "fsl,imx27-pwm"; 45 reg = <0x5d010000 0x10000>; 46 clock-names = "ipg", "per"; 47 clocks = <&pwm1_lpcg 4>, 48 <&pwm1_lpcg 1>; 49 assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; 50 assigned-clock-rates = <24000000>; 51 #pwm-cells = <2>; 52 status = "disabled"; 53 }; 54 55 lsio_pwm2: pwm@5d020000 { 56 compatible = "fsl,imx27-pwm"; 57 reg = <0x5d020000 0x10000>; 58 clock-names = "ipg", "per"; 59 clocks = <&pwm2_lpcg 4>, 60 <&pwm2_lpcg 1>; 61 assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; 62 assigned-clock-rates = <24000000>; 63 #pwm-cells = <2>; 64 status = "disabled"; 65 }; 66 67 lsio_pwm3: pwm@5d030000 { 68 compatible = "fsl,imx27-pwm"; 69 reg = <0x5d030000 0x10000>; 70 clock-names = "ipg", "per"; 71 clocks = <&pwm3_lpcg 4>, 72 <&pwm3_lpcg 1>; 73 assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; 74 assigned-clock-rates = <24000000>; 75 #pwm-cells = <2>; 76 status = "disabled"; 77 }; 78 79 lsio_gpio0: gpio@5d080000 { 80 reg = <0x5d080000 0x10000>; 81 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 82 gpio-controller; 83 #gpio-cells = <2>; 84 interrupt-controller; 85 #interrupt-cells = <2>; 86 power-domains = <&pd IMX_SC_R_GPIO_0>; 87 }; 88 89 lsio_gpio1: gpio@5d090000 { 90 reg = <0x5d090000 0x10000>; 91 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 92 gpio-controller; 93 #gpio-cells = <2>; 94 interrupt-controller; 95 #interrupt-cells = <2>; 96 power-domains = <&pd IMX_SC_R_GPIO_1>; 97 }; 98 99 lsio_gpio2: gpio@5d0a0000 { 100 reg = <0x5d0a0000 0x10000>; 101 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 102 gpio-controller; 103 #gpio-cells = <2>; 104 interrupt-controller; 105 #interrupt-cells = <2>; 106 power-domains = <&pd IMX_SC_R_GPIO_2>; 107 }; 108 109 lsio_gpio3: gpio@5d0b0000 { 110 reg = <0x5d0b0000 0x10000>; 111 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 112 gpio-controller; 113 #gpio-cells = <2>; 114 interrupt-controller; 115 #interrupt-cells = <2>; 116 power-domains = <&pd IMX_SC_R_GPIO_3>; 117 }; 118 119 lsio_gpio4: gpio@5d0c0000 { 120 reg = <0x5d0c0000 0x10000>; 121 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 122 gpio-controller; 123 #gpio-cells = <2>; 124 interrupt-controller; 125 #interrupt-cells = <2>; 126 power-domains = <&pd IMX_SC_R_GPIO_4>; 127 }; 128 129 lsio_gpio5: gpio@5d0d0000 { 130 reg = <0x5d0d0000 0x10000>; 131 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 132 gpio-controller; 133 #gpio-cells = <2>; 134 interrupt-controller; 135 #interrupt-cells = <2>; 136 power-domains = <&pd IMX_SC_R_GPIO_5>; 137 }; 138 139 lsio_gpio6: gpio@5d0e0000 { 140 reg = <0x5d0e0000 0x10000>; 141 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 142 gpio-controller; 143 #gpio-cells = <2>; 144 interrupt-controller; 145 #interrupt-cells = <2>; 146 power-domains = <&pd IMX_SC_R_GPIO_6>; 147 }; 148 149 lsio_gpio7: gpio@5d0f0000 { 150 reg = <0x5d0f0000 0x10000>; 151 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 152 gpio-controller; 153 #gpio-cells = <2>; 154 interrupt-controller; 155 #interrupt-cells = <2>; 156 power-domains = <&pd IMX_SC_R_GPIO_7>; 157 }; 158 159 flexspi0: spi@5d120000 { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 compatible = "nxp,imx8qxp-fspi"; 163 reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; 164 reg-names = "fspi_base", "fspi_mmap"; 165 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, 167 <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; 168 clock-names = "fspi_en", "fspi"; 169 power-domains = <&pd IMX_SC_R_FSPI_0>; 170 status = "disabled"; 171 }; 172 173 lsio_mu0: mailbox@5d1b0000 { 174 reg = <0x5d1b0000 0x10000>; 175 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 176 #mbox-cells = <2>; 177 status = "disabled"; 178 }; 179 180 lsio_mu1: mailbox@5d1c0000 { 181 reg = <0x5d1c0000 0x10000>; 182 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 183 #mbox-cells = <2>; 184 }; 185 186 lsio_mu2: mailbox@5d1d0000 { 187 reg = <0x5d1d0000 0x10000>; 188 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 189 #mbox-cells = <2>; 190 status = "disabled"; 191 }; 192 193 lsio_mu3: mailbox@5d1e0000 { 194 reg = <0x5d1e0000 0x10000>; 195 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 196 #mbox-cells = <2>; 197 status = "disabled"; 198 }; 199 200 lsio_mu4: mailbox@5d1f0000 { 201 reg = <0x5d1f0000 0x10000>; 202 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 203 #mbox-cells = <2>; 204 status = "disabled"; 205 }; 206 207 lsio_mu5: mailbox@5d200000 { 208 reg = <0x5d200000 0x10000>; 209 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 210 #mbox-cells = <2>; 211 power-domains = <&pd IMX_SC_R_MU_5A>; 212 status = "disabled"; 213 }; 214 215 lsio_mu6: mailbox@5d210000 { 216 reg = <0x5d210000 0x10000>; 217 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 218 #mbox-cells = <2>; 219 power-domains = <&pd IMX_SC_R_MU_6A>; 220 status = "disabled"; 221 }; 222 223 lsio_mu13: mailbox@5d280000 { 224 reg = <0x5d280000 0x10000>; 225 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 226 #mbox-cells = <2>; 227 power-domains = <&pd IMX_SC_R_MU_13A>; 228 }; 229 230 /* LPCG clocks */ 231 pwm0_lpcg: clock-controller@5d400000 { 232 compatible = "fsl,imx8qxp-lpcg"; 233 reg = <0x5d400000 0x10000>; 234 #clock-cells = <1>; 235 clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, 236 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, 237 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, 238 <&lsio_bus_clk>, 239 <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; 240 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 241 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 242 <IMX_LPCG_CLK_6>; 243 clock-output-names = "pwm0_lpcg_ipg_clk", 244 "pwm0_lpcg_ipg_hf_clk", 245 "pwm0_lpcg_ipg_s_clk", 246 "pwm0_lpcg_ipg_slv_clk", 247 "pwm0_lpcg_ipg_mstr_clk"; 248 power-domains = <&pd IMX_SC_R_PWM_0>; 249 }; 250 251 pwm1_lpcg: clock-controller@5d410000 { 252 compatible = "fsl,imx8qxp-lpcg"; 253 reg = <0x5d410000 0x10000>; 254 #clock-cells = <1>; 255 clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, 256 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, 257 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, 258 <&lsio_bus_clk>, 259 <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; 260 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 261 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 262 <IMX_LPCG_CLK_6>; 263 clock-output-names = "pwm1_lpcg_ipg_clk", 264 "pwm1_lpcg_ipg_hf_clk", 265 "pwm1_lpcg_ipg_s_clk", 266 "pwm1_lpcg_ipg_slv_clk", 267 "pwm1_lpcg_ipg_mstr_clk"; 268 power-domains = <&pd IMX_SC_R_PWM_1>; 269 }; 270 271 pwm2_lpcg: clock-controller@5d420000 { 272 compatible = "fsl,imx8qxp-lpcg"; 273 reg = <0x5d420000 0x10000>; 274 #clock-cells = <1>; 275 clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, 276 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, 277 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, 278 <&lsio_bus_clk>, 279 <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; 280 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 281 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 282 <IMX_LPCG_CLK_6>; 283 clock-output-names = "pwm2_lpcg_ipg_clk", 284 "pwm2_lpcg_ipg_hf_clk", 285 "pwm2_lpcg_ipg_s_clk", 286 "pwm2_lpcg_ipg_slv_clk", 287 "pwm2_lpcg_ipg_mstr_clk"; 288 power-domains = <&pd IMX_SC_R_PWM_2>; 289 }; 290 291 pwm3_lpcg: clock-controller@5d430000 { 292 compatible = "fsl,imx8qxp-lpcg"; 293 reg = <0x5d430000 0x10000>; 294 #clock-cells = <1>; 295 clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, 296 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, 297 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, 298 <&lsio_bus_clk>, 299 <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; 300 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 301 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 302 <IMX_LPCG_CLK_6>; 303 clock-output-names = "pwm3_lpcg_ipg_clk", 304 "pwm3_lpcg_ipg_hf_clk", 305 "pwm3_lpcg_ipg_s_clk", 306 "pwm3_lpcg_ipg_slv_clk", 307 "pwm3_lpcg_ipg_mstr_clk"; 308 power-domains = <&pd IMX_SC_R_PWM_3>; 309 }; 310 311 pwm4_lpcg: clock-controller@5d440000 { 312 compatible = "fsl,imx8qxp-lpcg"; 313 reg = <0x5d440000 0x10000>; 314 #clock-cells = <1>; 315 clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, 316 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, 317 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, 318 <&lsio_bus_clk>, 319 <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; 320 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 321 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 322 <IMX_LPCG_CLK_6>; 323 clock-output-names = "pwm4_lpcg_ipg_clk", 324 "pwm4_lpcg_ipg_hf_clk", 325 "pwm4_lpcg_ipg_s_clk", 326 "pwm4_lpcg_ipg_slv_clk", 327 "pwm4_lpcg_ipg_mstr_clk"; 328 power-domains = <&pd IMX_SC_R_PWM_4>; 329 }; 330 331 pwm5_lpcg: clock-controller@5d450000 { 332 compatible = "fsl,imx8qxp-lpcg"; 333 reg = <0x5d450000 0x10000>; 334 #clock-cells = <1>; 335 clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, 336 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, 337 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, 338 <&lsio_bus_clk>, 339 <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; 340 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 341 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 342 <IMX_LPCG_CLK_6>; 343 clock-output-names = "pwm5_lpcg_ipg_clk", 344 "pwm5_lpcg_ipg_hf_clk", 345 "pwm5_lpcg_ipg_s_clk", 346 "pwm5_lpcg_ipg_slv_clk", 347 "pwm5_lpcg_ipg_mstr_clk"; 348 power-domains = <&pd IMX_SC_R_PWM_5>; 349 }; 350 351 pwm6_lpcg: clock-controller@5d460000 { 352 compatible = "fsl,imx8qxp-lpcg"; 353 reg = <0x5d460000 0x10000>; 354 #clock-cells = <1>; 355 clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, 356 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, 357 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, 358 <&lsio_bus_clk>, 359 <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; 360 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 361 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 362 <IMX_LPCG_CLK_6>; 363 clock-output-names = "pwm6_lpcg_ipg_clk", 364 "pwm6_lpcg_ipg_hf_clk", 365 "pwm6_lpcg_ipg_s_clk", 366 "pwm6_lpcg_ipg_slv_clk", 367 "pwm6_lpcg_ipg_mstr_clk"; 368 power-domains = <&pd IMX_SC_R_PWM_6>; 369 }; 370 371 pwm7_lpcg: clock-controller@5d470000 { 372 compatible = "fsl,imx8qxp-lpcg"; 373 reg = <0x5d470000 0x10000>; 374 #clock-cells = <1>; 375 clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, 376 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, 377 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, 378 <&lsio_bus_clk>, 379 <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; 380 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 381 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 382 <IMX_LPCG_CLK_6>; 383 clock-output-names = "pwm7_lpcg_ipg_clk", 384 "pwm7_lpcg_ipg_hf_clk", 385 "pwm7_lpcg_ipg_s_clk", 386 "pwm7_lpcg_ipg_slv_clk", 387 "pwm7_lpcg_ipg_mstr_clk"; 388 power-domains = <&pd IMX_SC_R_PWM_7>; 389 }; 390}; 391