1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2024 NXP 4 * 5 * Richard Zhu <hongxing.zhu@nxp.com> 6 */ 7#include <dt-bindings/phy/phy.h> 8 9hsio_axi_clk: clock-hsio-axi { 10 compatible = "fixed-clock"; 11 #clock-cells = <0>; 12 clock-frequency = <400000000>; 13 clock-output-names = "hsio_axi_clk"; 14}; 15 16hsio_per_clk: clock-hsio-per { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 clock-frequency = <133333333>; 20 clock-output-names = "hsio_per_clk"; 21}; 22 23hsio_refa_clk: clock-hsio-refa { 24 compatible = "gpio-gate-clock"; 25 clocks = <&xtal100m>; 26 #clock-cells = <0>; 27 enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>; 28}; 29 30hsio_refb_clk: clock-hsio-refb { 31 compatible = "gpio-gate-clock"; 32 clocks = <&xtal100m>; 33 #clock-cells = <0>; 34 enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; 35}; 36 37xtal100m: clock-xtal100m { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <100000000>; 41 clock-output-names = "xtal_100MHz"; 42}; 43 44hsio_subsys: bus@5f000000 { 45 compatible = "simple-bus"; 46 ranges = <0x5f000000 0x0 0x5f000000 0x01000000>, 47 <0x80000000 0x0 0x70000000 0x10000000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 dma-ranges = <0x80000000 0 0x80000000 0x80000000>; 51 52 pcieb: pcie@5f010000 { 53 compatible = "fsl,imx8q-pcie"; 54 reg = <0x5f010000 0x10000>, 55 <0x8ff00000 0x80000>; 56 reg-names = "dbi", "config"; 57 ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, 58 <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; 59 #interrupt-cells = <1>; 60 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 61 interrupt-names = "msi"; 62 #address-cells = <3>; 63 #size-cells = <2>; 64 clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, 65 <&pcieb_lpcg IMX_LPCG_CLK_4>, 66 <&pcieb_lpcg IMX_LPCG_CLK_5>; 67 clock-names = "dbi", "mstr", "slv"; 68 bus-range = <0x00 0xff>; 69 device_type = "pci"; 70 interrupt-map = <0 0 0 1 &gic 0 105 4>, 71 <0 0 0 2 &gic 0 106 4>, 72 <0 0 0 3 &gic 0 107 4>, 73 <0 0 0 4 &gic 0 108 4>; 74 interrupt-map-mask = <0 0 0 0x7>; 75 num-lanes = <1>; 76 num-viewport = <4>; 77 power-domains = <&pd IMX_SC_R_PCIE_B>; 78 fsl,max-link-speed = <3>; 79 status = "disabled"; 80 }; 81 82 pcieb_lpcg: clock-controller@5f060000 { 83 compatible = "fsl,imx8qxp-lpcg"; 84 reg = <0x5f060000 0x10000>; 85 clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>; 86 #clock-cells = <1>; 87 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>; 88 clock-output-names = "hsio_pcieb_mstr_axi_clk", 89 "hsio_pcieb_slv_axi_clk", 90 "hsio_pcieb_dbi_axi_clk"; 91 power-domains = <&pd IMX_SC_R_PCIE_B>; 92 }; 93 94 phyx1_crr1_lpcg: clock-controller@5f0b0000 { 95 compatible = "fsl,imx8qxp-lpcg"; 96 reg = <0x5f0b0000 0x10000>; 97 clocks = <&hsio_per_clk>; 98 #clock-cells = <1>; 99 clock-indices = <IMX_LPCG_CLK_4>; 100 clock-output-names = "hsio_phyx1_per_clk"; 101 power-domains = <&pd IMX_SC_R_SERDES_1>; 102 }; 103 104 pcieb_crr3_lpcg: clock-controller@5f0d0000 { 105 compatible = "fsl,imx8qxp-lpcg"; 106 reg = <0x5f0d0000 0x10000>; 107 clocks = <&hsio_per_clk>; 108 #clock-cells = <1>; 109 clock-indices = <IMX_LPCG_CLK_4>; 110 clock-output-names = "hsio_pcieb_per_clk"; 111 power-domains = <&pd IMX_SC_R_PCIE_B>; 112 }; 113 114 misc_crr5_lpcg: clock-controller@5f0f0000 { 115 compatible = "fsl,imx8qxp-lpcg"; 116 reg = <0x5f0f0000 0x10000>; 117 clocks = <&hsio_per_clk>; 118 #clock-cells = <1>; 119 clock-indices = <IMX_LPCG_CLK_4>; 120 clock-output-names = "hsio_misc_per_clk"; 121 power-domains = <&pd IMX_SC_R_HSIO_GPIO>; 122 }; 123}; 124