1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10dma_ipg_clk: clock-dma-ipg { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <120000000>; 14 clock-output-names = "dma_ipg_clk"; 15}; 16 17dma_subsys: bus@5a000000 { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; 22 23 lpspi0: spi@5a000000 { 24 compatible = "fsl,imx7ulp-spi"; 25 reg = <0x5a000000 0x10000>; 26 #address-cells = <1>; 27 #size-cells = <0>; 28 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 29 interrupt-parent = <&gic>; 30 clocks = <&spi0_lpcg 0>, 31 <&spi0_lpcg 1>; 32 clock-names = "per", "ipg"; 33 assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; 34 assigned-clock-rates = <60000000>; 35 power-domains = <&pd IMX_SC_R_SPI_0>; 36 status = "disabled"; 37 }; 38 39 lpspi1: spi@5a010000 { 40 compatible = "fsl,imx7ulp-spi"; 41 reg = <0x5a010000 0x10000>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 45 interrupt-parent = <&gic>; 46 clocks = <&spi1_lpcg 0>, 47 <&spi1_lpcg 1>; 48 clock-names = "per", "ipg"; 49 assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; 50 assigned-clock-rates = <60000000>; 51 power-domains = <&pd IMX_SC_R_SPI_1>; 52 status = "disabled"; 53 }; 54 55 lpspi2: spi@5a020000 { 56 compatible = "fsl,imx7ulp-spi"; 57 reg = <0x5a020000 0x10000>; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 61 interrupt-parent = <&gic>; 62 clocks = <&spi2_lpcg 0>, 63 <&spi2_lpcg 1>; 64 clock-names = "per", "ipg"; 65 assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; 66 assigned-clock-rates = <60000000>; 67 power-domains = <&pd IMX_SC_R_SPI_2>; 68 status = "disabled"; 69 }; 70 71 lpspi3: spi@5a030000 { 72 compatible = "fsl,imx7ulp-spi"; 73 reg = <0x5a030000 0x10000>; 74 #address-cells = <1>; 75 #size-cells = <0>; 76 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 77 interrupt-parent = <&gic>; 78 clocks = <&spi3_lpcg 0>, 79 <&spi3_lpcg 1>; 80 clock-names = "per", "ipg"; 81 assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; 82 assigned-clock-rates = <60000000>; 83 power-domains = <&pd IMX_SC_R_SPI_3>; 84 status = "disabled"; 85 }; 86 87 lpuart0: serial@5a060000 { 88 reg = <0x5a060000 0x1000>; 89 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 90 clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, 91 <&uart0_lpcg IMX_LPCG_CLK_0>; 92 clock-names = "ipg", "baud"; 93 assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; 94 assigned-clock-rates = <80000000>; 95 power-domains = <&pd IMX_SC_R_UART_0>; 96 dma-names = "tx","rx"; 97 dmas = <&edma2 9 0 0>, <&edma2 8 0 1>; 98 status = "disabled"; 99 }; 100 101 lpuart1: serial@5a070000 { 102 reg = <0x5a070000 0x1000>; 103 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 104 clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, 105 <&uart1_lpcg IMX_LPCG_CLK_0>; 106 clock-names = "ipg", "baud"; 107 assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; 108 assigned-clock-rates = <80000000>; 109 power-domains = <&pd IMX_SC_R_UART_1>; 110 dma-names = "tx","rx"; 111 dmas = <&edma2 11 0 0>, <&edma2 10 0 1>; 112 status = "disabled"; 113 }; 114 115 lpuart2: serial@5a080000 { 116 reg = <0x5a080000 0x1000>; 117 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, 119 <&uart2_lpcg IMX_LPCG_CLK_0>; 120 clock-names = "ipg", "baud"; 121 assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; 122 assigned-clock-rates = <80000000>; 123 power-domains = <&pd IMX_SC_R_UART_2>; 124 dma-names = "tx","rx"; 125 dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; 126 status = "disabled"; 127 }; 128 129 lpuart3: serial@5a090000 { 130 reg = <0x5a090000 0x1000>; 131 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, 133 <&uart3_lpcg IMX_LPCG_CLK_0>; 134 clock-names = "ipg", "baud"; 135 assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; 136 assigned-clock-rates = <80000000>; 137 power-domains = <&pd IMX_SC_R_UART_3>; 138 dma-names = "tx","rx"; 139 dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; 140 status = "disabled"; 141 }; 142 143 adma_pwm: pwm@5a190000 { 144 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; 145 reg = <0x5a190000 0x1000>; 146 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&adma_pwm_lpcg 1>, 148 <&adma_pwm_lpcg 0>; 149 clock-names = "ipg", "per"; 150 assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; 151 assigned-clock-rates = <24000000>; 152 #pwm-cells = <2>; 153 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; 154 }; 155 156 edma2: dma-controller@5a1f0000 { 157 compatible = "fsl,imx8qm-edma"; 158 reg = <0x5a1f0000 0x170000>; 159 #dma-cells = <3>; 160 dma-channels = <16>; 161 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 177 power-domains = <&pd IMX_SC_R_DMA_2_CH0>, 178 <&pd IMX_SC_R_DMA_2_CH1>, 179 <&pd IMX_SC_R_DMA_2_CH2>, 180 <&pd IMX_SC_R_DMA_2_CH3>, 181 <&pd IMX_SC_R_DMA_2_CH4>, 182 <&pd IMX_SC_R_DMA_2_CH5>, 183 <&pd IMX_SC_R_DMA_2_CH6>, 184 <&pd IMX_SC_R_DMA_2_CH7>, 185 <&pd IMX_SC_R_DMA_2_CH8>, 186 <&pd IMX_SC_R_DMA_2_CH9>, 187 <&pd IMX_SC_R_DMA_2_CH10>, 188 <&pd IMX_SC_R_DMA_2_CH11>, 189 <&pd IMX_SC_R_DMA_2_CH12>, 190 <&pd IMX_SC_R_DMA_2_CH13>, 191 <&pd IMX_SC_R_DMA_2_CH14>, 192 <&pd IMX_SC_R_DMA_2_CH15>; 193 }; 194 195 edma3: dma-controller@5a9f0000 { 196 compatible = "fsl,imx8qm-edma"; 197 reg = <0x5a9f0000 0x90000>; 198 #dma-cells = <3>; 199 dma-channels = <8>; 200 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; 208 power-domains = <&pd IMX_SC_R_DMA_3_CH0>, 209 <&pd IMX_SC_R_DMA_3_CH1>, 210 <&pd IMX_SC_R_DMA_3_CH2>, 211 <&pd IMX_SC_R_DMA_3_CH3>, 212 <&pd IMX_SC_R_DMA_3_CH4>, 213 <&pd IMX_SC_R_DMA_3_CH5>, 214 <&pd IMX_SC_R_DMA_3_CH6>, 215 <&pd IMX_SC_R_DMA_3_CH7>; 216 }; 217 218 spi0_lpcg: clock-controller@5a400000 { 219 compatible = "fsl,imx8qxp-lpcg"; 220 reg = <0x5a400000 0x10000>; 221 #clock-cells = <1>; 222 clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, 223 <&dma_ipg_clk>; 224 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 225 clock-output-names = "spi0_lpcg_clk", 226 "spi0_lpcg_ipg_clk"; 227 power-domains = <&pd IMX_SC_R_SPI_0>; 228 }; 229 230 spi1_lpcg: clock-controller@5a410000 { 231 compatible = "fsl,imx8qxp-lpcg"; 232 reg = <0x5a410000 0x10000>; 233 #clock-cells = <1>; 234 clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, 235 <&dma_ipg_clk>; 236 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 237 clock-output-names = "spi1_lpcg_clk", 238 "spi1_lpcg_ipg_clk"; 239 power-domains = <&pd IMX_SC_R_SPI_1>; 240 }; 241 242 spi2_lpcg: clock-controller@5a420000 { 243 compatible = "fsl,imx8qxp-lpcg"; 244 reg = <0x5a420000 0x10000>; 245 #clock-cells = <1>; 246 clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, 247 <&dma_ipg_clk>; 248 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 249 clock-output-names = "spi2_lpcg_clk", 250 "spi2_lpcg_ipg_clk"; 251 power-domains = <&pd IMX_SC_R_SPI_2>; 252 }; 253 254 spi3_lpcg: clock-controller@5a430000 { 255 compatible = "fsl,imx8qxp-lpcg"; 256 reg = <0x5a430000 0x10000>; 257 #clock-cells = <1>; 258 clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, 259 <&dma_ipg_clk>; 260 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 261 clock-output-names = "spi3_lpcg_clk", 262 "spi3_lpcg_ipg_clk"; 263 power-domains = <&pd IMX_SC_R_SPI_3>; 264 }; 265 266 uart0_lpcg: clock-controller@5a460000 { 267 compatible = "fsl,imx8qxp-lpcg"; 268 reg = <0x5a460000 0x10000>; 269 #clock-cells = <1>; 270 clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, 271 <&dma_ipg_clk>; 272 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 273 clock-output-names = "uart0_lpcg_baud_clk", 274 "uart0_lpcg_ipg_clk"; 275 power-domains = <&pd IMX_SC_R_UART_0>; 276 }; 277 278 uart1_lpcg: clock-controller@5a470000 { 279 compatible = "fsl,imx8qxp-lpcg"; 280 reg = <0x5a470000 0x10000>; 281 #clock-cells = <1>; 282 clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, 283 <&dma_ipg_clk>; 284 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 285 clock-output-names = "uart1_lpcg_baud_clk", 286 "uart1_lpcg_ipg_clk"; 287 power-domains = <&pd IMX_SC_R_UART_1>; 288 }; 289 290 uart2_lpcg: clock-controller@5a480000 { 291 compatible = "fsl,imx8qxp-lpcg"; 292 reg = <0x5a480000 0x10000>; 293 #clock-cells = <1>; 294 clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, 295 <&dma_ipg_clk>; 296 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 297 clock-output-names = "uart2_lpcg_baud_clk", 298 "uart2_lpcg_ipg_clk"; 299 power-domains = <&pd IMX_SC_R_UART_2>; 300 }; 301 302 uart3_lpcg: clock-controller@5a490000 { 303 compatible = "fsl,imx8qxp-lpcg"; 304 reg = <0x5a490000 0x10000>; 305 #clock-cells = <1>; 306 clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, 307 <&dma_ipg_clk>; 308 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 309 clock-output-names = "uart3_lpcg_baud_clk", 310 "uart3_lpcg_ipg_clk"; 311 power-domains = <&pd IMX_SC_R_UART_3>; 312 }; 313 314 adma_pwm_lpcg: clock-controller@5a590000 { 315 compatible = "fsl,imx8qxp-lpcg"; 316 reg = <0x5a590000 0x10000>; 317 #clock-cells = <1>; 318 clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>, 319 <&dma_ipg_clk>; 320 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 321 clock-output-names = "adma_pwm_lpcg_clk", 322 "adma_pwm_lpcg_ipg_clk"; 323 power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; 324 }; 325 326 i2c0: i2c@5a800000 { 327 reg = <0x5a800000 0x4000>; 328 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&i2c0_lpcg IMX_LPCG_CLK_0>, 330 <&i2c0_lpcg IMX_LPCG_CLK_4>; 331 clock-names = "per", "ipg"; 332 assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; 333 assigned-clock-rates = <24000000>; 334 power-domains = <&pd IMX_SC_R_I2C_0>; 335 status = "disabled"; 336 }; 337 338 i2c1: i2c@5a810000 { 339 reg = <0x5a810000 0x4000>; 340 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&i2c1_lpcg IMX_LPCG_CLK_0>, 342 <&i2c1_lpcg IMX_LPCG_CLK_4>; 343 clock-names = "per", "ipg"; 344 assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; 345 assigned-clock-rates = <24000000>; 346 power-domains = <&pd IMX_SC_R_I2C_1>; 347 status = "disabled"; 348 }; 349 350 i2c2: i2c@5a820000 { 351 reg = <0x5a820000 0x4000>; 352 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&i2c2_lpcg IMX_LPCG_CLK_0>, 354 <&i2c2_lpcg IMX_LPCG_CLK_4>; 355 clock-names = "per", "ipg"; 356 assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; 357 assigned-clock-rates = <24000000>; 358 power-domains = <&pd IMX_SC_R_I2C_2>; 359 status = "disabled"; 360 }; 361 362 i2c3: i2c@5a830000 { 363 reg = <0x5a830000 0x4000>; 364 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&i2c3_lpcg IMX_LPCG_CLK_0>, 366 <&i2c3_lpcg IMX_LPCG_CLK_4>; 367 clock-names = "per", "ipg"; 368 assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; 369 assigned-clock-rates = <24000000>; 370 power-domains = <&pd IMX_SC_R_I2C_3>; 371 status = "disabled"; 372 }; 373 374 adc0: adc@5a880000 { 375 compatible = "nxp,imx8qxp-adc"; 376 #io-channel-cells = <1>; 377 reg = <0x5a880000 0x10000>; 378 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 379 interrupt-parent = <&gic>; 380 clocks = <&adc0_lpcg 0>, 381 <&adc0_lpcg 1>; 382 clock-names = "per", "ipg"; 383 assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; 384 assigned-clock-rates = <24000000>; 385 power-domains = <&pd IMX_SC_R_ADC_0>; 386 status = "disabled"; 387 }; 388 389 adc1: adc@5a890000 { 390 compatible = "nxp,imx8qxp-adc"; 391 #io-channel-cells = <1>; 392 reg = <0x5a890000 0x10000>; 393 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 394 interrupt-parent = <&gic>; 395 clocks = <&adc1_lpcg 0>, 396 <&adc1_lpcg 1>; 397 clock-names = "per", "ipg"; 398 assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; 399 assigned-clock-rates = <24000000>; 400 power-domains = <&pd IMX_SC_R_ADC_1>; 401 status = "disabled"; 402 }; 403 404 flexcan1: can@5a8d0000 { 405 compatible = "fsl,imx8qm-flexcan"; 406 reg = <0x5a8d0000 0x10000>; 407 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 408 interrupt-parent = <&gic>; 409 clocks = <&can0_lpcg 1>, 410 <&can0_lpcg 0>; 411 clock-names = "ipg", "per"; 412 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 413 assigned-clock-rates = <40000000>; 414 power-domains = <&pd IMX_SC_R_CAN_0>; 415 /* SLSlice[4] */ 416 fsl,clk-source = /bits/ 8 <0>; 417 fsl,scu-index = /bits/ 8 <0>; 418 status = "disabled"; 419 }; 420 421 flexcan2: can@5a8e0000 { 422 compatible = "fsl,imx8qm-flexcan"; 423 reg = <0x5a8e0000 0x10000>; 424 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 425 interrupt-parent = <&gic>; 426 /* CAN0 clock and PD is shared among all CAN instances as 427 * CAN1 shares CAN0's clock and to enable CAN0's clock it 428 * has to be powered on. 429 */ 430 clocks = <&can0_lpcg 1>, 431 <&can0_lpcg 0>; 432 clock-names = "ipg", "per"; 433 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 434 assigned-clock-rates = <40000000>; 435 power-domains = <&pd IMX_SC_R_CAN_1>; 436 /* SLSlice[4] */ 437 fsl,clk-source = /bits/ 8 <0>; 438 fsl,scu-index = /bits/ 8 <1>; 439 status = "disabled"; 440 }; 441 442 flexcan3: can@5a8f0000 { 443 compatible = "fsl,imx8qm-flexcan"; 444 reg = <0x5a8f0000 0x10000>; 445 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-parent = <&gic>; 447 /* CAN0 clock and PD is shared among all CAN instances as 448 * CAN2 shares CAN0's clock and to enable CAN0's clock it 449 * has to be powered on. 450 */ 451 clocks = <&can0_lpcg 1>, 452 <&can0_lpcg 0>; 453 clock-names = "ipg", "per"; 454 assigned-clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>; 455 assigned-clock-rates = <40000000>; 456 power-domains = <&pd IMX_SC_R_CAN_2>; 457 /* SLSlice[4] */ 458 fsl,clk-source = /bits/ 8 <0>; 459 fsl,scu-index = /bits/ 8 <2>; 460 status = "disabled"; 461 }; 462 463 i2c0_lpcg: clock-controller@5ac00000 { 464 compatible = "fsl,imx8qxp-lpcg"; 465 reg = <0x5ac00000 0x10000>; 466 #clock-cells = <1>; 467 clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, 468 <&dma_ipg_clk>; 469 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 470 clock-output-names = "i2c0_lpcg_clk", 471 "i2c0_lpcg_ipg_clk"; 472 power-domains = <&pd IMX_SC_R_I2C_0>; 473 }; 474 475 i2c1_lpcg: clock-controller@5ac10000 { 476 compatible = "fsl,imx8qxp-lpcg"; 477 reg = <0x5ac10000 0x10000>; 478 #clock-cells = <1>; 479 clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, 480 <&dma_ipg_clk>; 481 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 482 clock-output-names = "i2c1_lpcg_clk", 483 "i2c1_lpcg_ipg_clk"; 484 power-domains = <&pd IMX_SC_R_I2C_1>; 485 }; 486 487 i2c2_lpcg: clock-controller@5ac20000 { 488 compatible = "fsl,imx8qxp-lpcg"; 489 reg = <0x5ac20000 0x10000>; 490 #clock-cells = <1>; 491 clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, 492 <&dma_ipg_clk>; 493 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 494 clock-output-names = "i2c2_lpcg_clk", 495 "i2c2_lpcg_ipg_clk"; 496 power-domains = <&pd IMX_SC_R_I2C_2>; 497 }; 498 499 i2c3_lpcg: clock-controller@5ac30000 { 500 compatible = "fsl,imx8qxp-lpcg"; 501 reg = <0x5ac30000 0x10000>; 502 #clock-cells = <1>; 503 clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, 504 <&dma_ipg_clk>; 505 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 506 clock-output-names = "i2c3_lpcg_clk", 507 "i2c3_lpcg_ipg_clk"; 508 power-domains = <&pd IMX_SC_R_I2C_3>; 509 }; 510 511 adc0_lpcg: clock-controller@5ac80000 { 512 compatible = "fsl,imx8qxp-lpcg"; 513 reg = <0x5ac80000 0x10000>; 514 #clock-cells = <1>; 515 clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, 516 <&dma_ipg_clk>; 517 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 518 clock-output-names = "adc0_lpcg_clk", 519 "adc0_lpcg_ipg_clk"; 520 power-domains = <&pd IMX_SC_R_ADC_0>; 521 }; 522 523 adc1_lpcg: clock-controller@5ac90000 { 524 compatible = "fsl,imx8qxp-lpcg"; 525 reg = <0x5ac90000 0x10000>; 526 #clock-cells = <1>; 527 clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, 528 <&dma_ipg_clk>; 529 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 530 clock-output-names = "adc1_lpcg_clk", 531 "adc1_lpcg_ipg_clk"; 532 power-domains = <&pd IMX_SC_R_ADC_1>; 533 }; 534 535 can0_lpcg: clock-controller@5acd0000 { 536 compatible = "fsl,imx8qxp-lpcg"; 537 reg = <0x5acd0000 0x10000>; 538 #clock-cells = <1>; 539 clocks = <&clk IMX_SC_R_CAN_0 IMX_SC_PM_CLK_PER>, 540 <&dma_ipg_clk>, <&dma_ipg_clk>; 541 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 542 clock-output-names = "can0_lpcg_pe_clk", 543 "can0_lpcg_ipg_clk", 544 "can0_lpcg_chi_clk"; 545 power-domains = <&pd IMX_SC_R_CAN_0>; 546 }; 547}; 548