1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10conn_subsys: bus@5b000000 { 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 15 16 conn_axi_clk: clock-conn-axi { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 clock-frequency = <333333333>; 20 clock-output-names = "conn_axi_clk"; 21 }; 22 23 conn_ahb_clk: clock-conn-ahb { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <166666666>; 27 clock-output-names = "conn_ahb_clk"; 28 }; 29 30 conn_ipg_clk: clock-conn-ipg { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <83333333>; 34 clock-output-names = "conn_ipg_clk"; 35 }; 36 37 usdhc1: mmc@5b010000 { 38 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 39 reg = <0x5b010000 0x10000>; 40 clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, 41 <&sdhc0_lpcg IMX_LPCG_CLK_5>, 42 <&sdhc0_lpcg IMX_LPCG_CLK_0>; 43 clock-names = "ipg", "per", "ahb"; 44 power-domains = <&pd IMX_SC_R_SDHC_0>; 45 status = "disabled"; 46 }; 47 48 usdhc2: mmc@5b020000 { 49 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 50 reg = <0x5b020000 0x10000>; 51 clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>, 52 <&sdhc1_lpcg IMX_LPCG_CLK_5>, 53 <&sdhc1_lpcg IMX_LPCG_CLK_0>; 54 clock-names = "ipg", "per", "ahb"; 55 power-domains = <&pd IMX_SC_R_SDHC_1>; 56 fsl,tuning-start-tap = <20>; 57 fsl,tuning-step= <2>; 58 status = "disabled"; 59 }; 60 61 usdhc3: mmc@5b030000 { 62 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 63 reg = <0x5b030000 0x10000>; 64 clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>, 65 <&sdhc2_lpcg IMX_LPCG_CLK_5>, 66 <&sdhc2_lpcg IMX_LPCG_CLK_0>; 67 clock-names = "ipg", "per", "ahb"; 68 power-domains = <&pd IMX_SC_R_SDHC_2>; 69 status = "disabled"; 70 }; 71 72 fec1: ethernet@5b040000 { 73 reg = <0x5b040000 0x10000>; 74 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&enet0_lpcg IMX_LPCG_CLK_4>, 79 <&enet0_lpcg IMX_LPCG_CLK_2>, 80 <&enet0_lpcg IMX_LPCG_CLK_1>, 81 <&enet0_lpcg IMX_LPCG_CLK_0>; 82 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 83 fsl,num-tx-queues=<3>; 84 fsl,num-rx-queues=<3>; 85 power-domains = <&pd IMX_SC_R_ENET_0>; 86 status = "disabled"; 87 }; 88 89 fec2: ethernet@5b050000 { 90 reg = <0x5b050000 0x10000>; 91 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&enet1_lpcg IMX_LPCG_CLK_4>, 96 <&enet1_lpcg IMX_LPCG_CLK_2>, 97 <&enet1_lpcg IMX_LPCG_CLK_1>, 98 <&enet1_lpcg IMX_LPCG_CLK_0>; 99 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 100 fsl,num-tx-queues=<3>; 101 fsl,num-rx-queues=<3>; 102 power-domains = <&pd IMX_SC_R_ENET_1>; 103 status = "disabled"; 104 }; 105 106 /* LPCG clocks */ 107 sdhc0_lpcg: clock-controller@5b200000 { 108 compatible = "fsl,imx8qxp-lpcg"; 109 reg = <0x5b200000 0x10000>; 110 #clock-cells = <1>; 111 clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, 112 <&conn_ipg_clk>, <&conn_axi_clk>; 113 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 114 <IMX_LPCG_CLK_5>; 115 clock-output-names = "sdhc0_lpcg_per_clk", 116 "sdhc0_lpcg_ipg_clk", 117 "sdhc0_lpcg_ahb_clk"; 118 power-domains = <&pd IMX_SC_R_SDHC_0>; 119 }; 120 121 sdhc1_lpcg: clock-controller@5b210000 { 122 compatible = "fsl,imx8qxp-lpcg"; 123 reg = <0x5b210000 0x10000>; 124 #clock-cells = <1>; 125 clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, 126 <&conn_ipg_clk>, <&conn_axi_clk>; 127 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 128 <IMX_LPCG_CLK_5>; 129 clock-output-names = "sdhc1_lpcg_per_clk", 130 "sdhc1_lpcg_ipg_clk", 131 "sdhc1_lpcg_ahb_clk"; 132 power-domains = <&pd IMX_SC_R_SDHC_1>; 133 }; 134 135 sdhc2_lpcg: clock-controller@5b220000 { 136 compatible = "fsl,imx8qxp-lpcg"; 137 reg = <0x5b220000 0x10000>; 138 #clock-cells = <1>; 139 clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, 140 <&conn_ipg_clk>, <&conn_axi_clk>; 141 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, 142 <IMX_LPCG_CLK_5>; 143 clock-output-names = "sdhc2_lpcg_per_clk", 144 "sdhc2_lpcg_ipg_clk", 145 "sdhc2_lpcg_ahb_clk"; 146 power-domains = <&pd IMX_SC_R_SDHC_2>; 147 }; 148 149 enet0_lpcg: clock-controller@5b230000 { 150 compatible = "fsl,imx8qxp-lpcg"; 151 reg = <0x5b230000 0x10000>; 152 #clock-cells = <1>; 153 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 154 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, 155 <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; 156 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 157 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>, 158 <IMX_LPCG_CLK_5>; 159 clock-output-names = "enet0_ipg_root_clk", 160 "enet0_tx_clk", 161 "enet0_ahb_clk", 162 "enet0_ipg_clk", 163 "enet0_ipg_s_clk"; 164 power-domains = <&pd IMX_SC_R_ENET_0>; 165 }; 166 167 enet1_lpcg: clock-controller@5b240000 { 168 compatible = "fsl,imx8qxp-lpcg"; 169 reg = <0x5b240000 0x10000>; 170 #clock-cells = <1>; 171 clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 172 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, 173 <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; 174 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 175 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>, 176 <IMX_LPCG_CLK_5>; 177 clock-output-names = "enet1_ipg_root_clk", 178 "enet1_tx_clk", 179 "enet1_ahb_clk", 180 "enet1_ipg_clk", 181 "enet1_ipg_s_clk"; 182 power-domains = <&pd IMX_SC_R_ENET_1>; 183 }; 184}; 185