1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2024 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/firmware/imx/rsrc.h> 8 9cm40_ipg_clk: clock-cm40-ipg { 10 compatible = "fixed-clock"; 11 #clock-cells = <0>; 12 clock-frequency = <132000000>; 13 clock-output-names = "cm40_ipg_clk"; 14}; 15 16cm40_subsys: bus@34000000 { 17 compatible = "simple-bus"; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 ranges = <0x34000000 0x0 0x34000000 0x4000000>; 21 interrupt-parent = <&cm40_intmux>; 22 23 cm40_lpuart: serial@37220000 { 24 compatible = "fsl,imx8qxp-lpuart"; 25 reg = <0x37220000 0x1000>; 26 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; 27 clocks = <&cm40_uart_lpcg IMX_LPCG_CLK_1>, <&cm40_uart_lpcg IMX_LPCG_CLK_0>; 28 clock-names = "ipg", "baud"; 29 assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>; 30 assigned-clock-rates = <24000000>; 31 power-domains = <&pd IMX_SC_R_M4_0_UART>; 32 status = "disabled"; 33 }; 34 35 cm40_i2c: i2c@37230000 { 36 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 37 reg = <0x37230000 0x1000>; 38 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 39 clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>, 40 <&cm40_i2c_lpcg IMX_LPCG_CLK_4>; 41 clock-names = "per", "ipg"; 42 assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>; 43 assigned-clock-rates = <24000000>; 44 power-domains = <&pd IMX_SC_R_M4_0_I2C>; 45 status = "disabled"; 46 }; 47 48 cm40_intmux: intmux@37400000 { 49 compatible = "fsl,imx-intmux"; 50 reg = <0x37400000 0x1000>; 51 interrupt-parent = <&gic>; 52 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 60 interrupt-controller; 61 #interrupt-cells = <2>; 62 clocks = <&cm40_ipg_clk>; 63 clock-names = "ipg"; 64 power-domains = <&pd IMX_SC_R_M4_0_INTMUX>; 65 status = "disabled"; 66 }; 67 68 cm40_uart_lpcg: clock-controller@37620000 { 69 compatible = "fsl,imx8qxp-lpcg"; 70 reg = <0x37620000 0x1000>; 71 #clock-cells = <1>; 72 clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>, 73 <&cm40_ipg_clk>; 74 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>; 75 clock-output-names = "cm40_lpcg_uart_clk", 76 "cm40_lpcg_uart_ipg_clk"; 77 power-domains = <&pd IMX_SC_R_M4_0_UART>; 78 }; 79 80 cm40_i2c_lpcg: clock-controller@37630000 { 81 compatible = "fsl,imx8qxp-lpcg"; 82 reg = <0x37630000 0x1000>; 83 #clock-cells = <1>; 84 clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>, 85 <&cm40_ipg_clk>; 86 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 87 clock-output-names = "cm40_lpcg_i2c_clk", 88 "cm40_lpcg_i2c_ipg_clk"; 89 power-domains = <&pd IMX_SC_R_M4_0_I2C>; 90 }; 91}; 92