1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-clock.h> 8#include <dt-bindings/clock/imx8-lpcg.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10 11audio_ipg_clk: clock-audio-ipg { 12 compatible = "fixed-clock"; 13 #clock-cells = <0>; 14 clock-frequency = <120000000>; 15 clock-output-names = "audio_ipg_clk"; 16}; 17 18clk_ext_aud_mclk0: clock-ext-aud-mclk0 { 19 compatible = "fixed-clock"; 20 #clock-cells = <0>; 21 clock-frequency = <0>; 22 clock-output-names = "ext_aud_mclk0"; 23}; 24 25clk_ext_aud_mclk1: clock-ext-aud-mclk1 { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <0>; 29 clock-output-names = "ext_aud_mclk1"; 30}; 31 32clk_esai0_rx_clk: clock-esai0-rx { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <0>; 36 clock-output-names = "esai0_rx_clk"; 37}; 38 39clk_esai0_rx_hf_clk: clock-esai0-rx-hf { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <0>; 43 clock-output-names = "esai0_rx_hf_clk"; 44}; 45 46clk_esai0_tx_clk: clock-esai0-tx { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 clock-output-names = "esai0_tx_clk"; 51}; 52 53clk_esai0_tx_hf_clk: clock-esai0-tx-hf { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <0>; 57 clock-output-names = "esai0_tx_hf_clk"; 58}; 59 60clk_spdif0_rx: clock-spdif0-rx { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <0>; 64 clock-output-names = "spdif0_rx"; 65}; 66 67clk_sai0_rx_bclk: clock-sai0-rx-bclk { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <0>; 71 clock-output-names = "sai0_rx_bclk"; 72}; 73 74clk_sai0_tx_bclk: clock-sai0-tx-bclk { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <0>; 78 clock-output-names = "sai0_tx_bclk"; 79}; 80 81clk_sai1_rx_bclk: clock-sai1-rx-bclk { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 clock-output-names = "sai1_rx_bclk"; 86}; 87 88clk_sai1_tx_bclk: clock-sai1-tx-bclk { 89 compatible = "fixed-clock"; 90 #clock-cells = <0>; 91 clock-frequency = <0>; 92 clock-output-names = "sai1_tx_bclk"; 93}; 94 95clk_sai2_rx_bclk: clock-sai2-rx-bclk { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <0>; 99 clock-output-names = "sai2_rx_bclk"; 100}; 101 102clk_sai3_rx_bclk: clock-sai3-rx-bclk { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 clock-frequency = <0>; 106 clock-output-names = "sai3_rx_bclk"; 107}; 108 109clk_sai4_rx_bclk: clock-sai4-rx-bclk { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <0>; 113 clock-output-names = "sai4_rx_bclk"; 114}; 115 116audio_subsys: bus@59000000 { 117 compatible = "simple-bus"; 118 #address-cells = <1>; 119 #size-cells = <1>; 120 ranges = <0x59000000 0x0 0x59000000 0x1000000>; 121 122 sai0: sai@59040000 { 123 compatible = "fsl,imx8qm-sai"; 124 reg = <0x59040000 0x10000>; 125 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&sai0_lpcg 1>, 127 <&clk_dummy>, 128 <&sai0_lpcg 0>, 129 <&clk_dummy>, 130 <&clk_dummy>; 131 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 132 dma-names = "rx", "tx"; 133 dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; 134 power-domains = <&pd IMX_SC_R_SAI_0>; 135 status = "disabled"; 136 }; 137 138 sai1: sai@59050000 { 139 compatible = "fsl,imx8qm-sai"; 140 reg = <0x59050000 0x10000>; 141 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&sai1_lpcg 1>, 143 <&clk_dummy>, 144 <&sai1_lpcg 0>, 145 <&clk_dummy>, 146 <&clk_dummy>; 147 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 148 dma-names = "rx", "tx"; 149 dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; 150 power-domains = <&pd IMX_SC_R_SAI_1>; 151 status = "disabled"; 152 }; 153 154 sai2: sai@59060000 { 155 compatible = "fsl,imx8qm-sai"; 156 reg = <0x59060000 0x10000>; 157 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&sai2_lpcg 1>, 159 <&clk_dummy>, 160 <&sai2_lpcg 0>, 161 <&clk_dummy>, 162 <&clk_dummy>; 163 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 164 dma-names = "rx"; 165 dmas = <&edma0 16 0 1>; 166 power-domains = <&pd IMX_SC_R_SAI_2>; 167 status = "disabled"; 168 }; 169 170 sai3: sai@59070000 { 171 compatible = "fsl,imx8qm-sai"; 172 reg = <0x59070000 0x10000>; 173 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&sai3_lpcg 1>, 175 <&clk_dummy>, 176 <&sai3_lpcg 0>, 177 <&clk_dummy>, 178 <&clk_dummy>; 179 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 180 dma-names = "rx"; 181 dmas = <&edma0 17 0 1>; 182 power-domains = <&pd IMX_SC_R_SAI_3>; 183 status = "disabled"; 184 }; 185 186 edma0: dma-controller@591f0000 { 187 compatible = "fsl,imx8qm-edma"; 188 reg = <0x591f0000 0x190000>; 189 #dma-cells = <3>; 190 dma-channels = <24>; 191 dma-channel-mask = <0x5c0c00>; 192 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */ 193 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 194 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 195 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 196 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 197 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 198 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */ 199 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */ 200 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */ 201 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */ 202 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */ 203 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */ 204 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */ 205 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */ 206 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */ 207 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */ 208 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */ 209 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */ 210 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */ 211 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */ 212 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */ 213 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */ 214 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */ 215 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */ 216 power-domains = <&pd IMX_SC_R_DMA_0_CH0>, 217 <&pd IMX_SC_R_DMA_0_CH1>, 218 <&pd IMX_SC_R_DMA_0_CH2>, 219 <&pd IMX_SC_R_DMA_0_CH3>, 220 <&pd IMX_SC_R_DMA_0_CH4>, 221 <&pd IMX_SC_R_DMA_0_CH5>, 222 <&pd IMX_SC_R_DMA_0_CH6>, 223 <&pd IMX_SC_R_DMA_0_CH7>, 224 <&pd IMX_SC_R_DMA_0_CH8>, 225 <&pd IMX_SC_R_DMA_0_CH9>, 226 <&pd IMX_SC_R_DMA_0_CH10>, 227 <&pd IMX_SC_R_DMA_0_CH11>, 228 <&pd IMX_SC_R_DMA_0_CH12>, 229 <&pd IMX_SC_R_DMA_0_CH13>, 230 <&pd IMX_SC_R_DMA_0_CH14>, 231 <&pd IMX_SC_R_DMA_0_CH15>, 232 <&pd IMX_SC_R_DMA_0_CH16>, 233 <&pd IMX_SC_R_DMA_0_CH17>, 234 <&pd IMX_SC_R_DMA_0_CH18>, 235 <&pd IMX_SC_R_DMA_0_CH19>, 236 <&pd IMX_SC_R_DMA_0_CH20>, 237 <&pd IMX_SC_R_DMA_0_CH21>, 238 <&pd IMX_SC_R_DMA_0_CH22>, 239 <&pd IMX_SC_R_DMA_0_CH23>; 240 }; 241 242 sai0_lpcg: clock-controller@59440000 { 243 compatible = "fsl,imx8qxp-lpcg"; 244 reg = <0x59440000 0x10000>; 245 #clock-cells = <1>; 246 clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, 247 <&audio_ipg_clk>; 248 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 249 clock-output-names = "sai0_lpcg_mclk", 250 "sai0_lpcg_ipg_clk"; 251 power-domains = <&pd IMX_SC_R_SAI_0>; 252 }; 253 254 sai1_lpcg: clock-controller@59450000 { 255 compatible = "fsl,imx8qxp-lpcg"; 256 reg = <0x59450000 0x10000>; 257 #clock-cells = <1>; 258 clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, 259 <&audio_ipg_clk>; 260 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 261 clock-output-names = "sai1_lpcg_mclk", 262 "sai1_lpcg_ipg_clk"; 263 power-domains = <&pd IMX_SC_R_SAI_1>; 264 }; 265 266 sai2_lpcg: clock-controller@59460000 { 267 compatible = "fsl,imx8qxp-lpcg"; 268 reg = <0x59460000 0x10000>; 269 #clock-cells = <1>; 270 clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>, 271 <&audio_ipg_clk>; 272 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 273 clock-output-names = "sai2_lpcg_mclk", 274 "sai2_lpcg_ipg_clk"; 275 power-domains = <&pd IMX_SC_R_SAI_2>; 276 }; 277 278 sai3_lpcg: clock-controller@59470000 { 279 compatible = "fsl,imx8qxp-lpcg"; 280 reg = <0x59470000 0x10000>; 281 #clock-cells = <1>; 282 clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>, 283 <&audio_ipg_clk>; 284 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 285 clock-output-names = "sai3_lpcg_mclk", 286 "sai3_lpcg_ipg_clk"; 287 power-domains = <&pd IMX_SC_R_SAI_3>; 288 }; 289 290 dsp_lpcg: clock-controller@59580000 { 291 compatible = "fsl,imx8qxp-lpcg"; 292 reg = <0x59580000 0x10000>; 293 #clock-cells = <1>; 294 clocks = <&audio_ipg_clk>, 295 <&audio_ipg_clk>, 296 <&audio_ipg_clk>; 297 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 298 <IMX_LPCG_CLK_7>; 299 clock-output-names = "dsp_lpcg_adb_clk", 300 "dsp_lpcg_ipg_clk", 301 "dsp_lpcg_core_clk"; 302 power-domains = <&pd IMX_SC_R_DSP>; 303 }; 304 305 dsp_ram_lpcg: clock-controller@59590000 { 306 compatible = "fsl,imx8qxp-lpcg"; 307 reg = <0x59590000 0x10000>; 308 #clock-cells = <1>; 309 clocks = <&audio_ipg_clk>; 310 clock-indices = <IMX_LPCG_CLK_4>; 311 clock-output-names = "dsp_ram_lpcg_ipg_clk"; 312 power-domains = <&pd IMX_SC_R_DSP_RAM>; 313 }; 314 315 dsp: dsp@596e8000 { 316 compatible = "fsl,imx8qxp-dsp"; 317 reg = <0x596e8000 0x88000>; 318 clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, 319 <&dsp_ram_lpcg IMX_LPCG_CLK_4>, 320 <&dsp_lpcg IMX_LPCG_CLK_7>; 321 clock-names = "ipg", "ocram", "core"; 322 power-domains = <&pd IMX_SC_R_MU_13A>, 323 <&pd IMX_SC_R_MU_13B>, 324 <&pd IMX_SC_R_DSP>, 325 <&pd IMX_SC_R_DSP_RAM>; 326 mbox-names = "txdb0", "txdb1", 327 "rxdb0", "rxdb1"; 328 mboxes = <&lsio_mu13 2 0>, 329 <&lsio_mu13 2 1>, 330 <&lsio_mu13 3 0>, 331 <&lsio_mu13 3 1>; 332 memory-region = <&dsp_reserved>; 333 status = "disabled"; 334 }; 335 336 edma1: dma-controller@599f0000 { 337 compatible = "fsl,imx8qm-edma"; 338 reg = <0x599f0000 0xc0000>; 339 #dma-cells = <3>; 340 dma-channels = <11>; 341 dma-channel-mask = <0xc0>; 342 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */ 343 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 344 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 345 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 346 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 347 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 348 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */ 349 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */ 350 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ 351 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ 353 power-domains = <&pd IMX_SC_R_DMA_1_CH0>, 354 <&pd IMX_SC_R_DMA_1_CH1>, 355 <&pd IMX_SC_R_DMA_1_CH2>, 356 <&pd IMX_SC_R_DMA_1_CH3>, 357 <&pd IMX_SC_R_DMA_1_CH4>, 358 <&pd IMX_SC_R_DMA_1_CH5>, 359 <&pd IMX_SC_R_DMA_1_CH6>, 360 <&pd IMX_SC_R_DMA_1_CH7>, 361 <&pd IMX_SC_R_DMA_1_CH8>, 362 <&pd IMX_SC_R_DMA_1_CH9>, 363 <&pd IMX_SC_R_DMA_1_CH10>; 364 }; 365 366 aud_rec0_lpcg: clock-controller@59d00000 { 367 compatible = "fsl,imx8qxp-lpcg"; 368 reg = <0x59d00000 0x10000>; 369 #clock-cells = <1>; 370 clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; 371 clock-indices = <IMX_LPCG_CLK_0>; 372 clock-output-names = "aud_rec_clk0_lpcg_clk"; 373 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; 374 }; 375 376 aud_rec1_lpcg: clock-controller@59d10000 { 377 compatible = "fsl,imx8qxp-lpcg"; 378 reg = <0x59d10000 0x10000>; 379 #clock-cells = <1>; 380 clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>; 381 clock-indices = <IMX_LPCG_CLK_0>; 382 clock-output-names = "aud_rec_clk1_lpcg_clk"; 383 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; 384 }; 385 386 aud_pll_div0_lpcg: clock-controller@59d20000 { 387 compatible = "fsl,imx8qxp-lpcg"; 388 reg = <0x59d20000 0x10000>; 389 #clock-cells = <1>; 390 clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>; 391 clock-indices = <IMX_LPCG_CLK_0>; 392 clock-output-names = "aud_pll_div_clk0_lpcg_clk"; 393 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; 394 }; 395 396 aud_pll_div1_lpcg: clock-controller@59d30000 { 397 compatible = "fsl,imx8qxp-lpcg"; 398 reg = <0x59d30000 0x10000>; 399 #clock-cells = <1>; 400 clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>; 401 clock-indices = <IMX_LPCG_CLK_0>; 402 clock-output-names = "aud_pll_div_clk1_lpcg_clk"; 403 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; 404 }; 405 406 mclkout0_lpcg: clock-controller@59d50000 { 407 compatible = "fsl,imx8qxp-lpcg"; 408 reg = <0x59d50000 0x10000>; 409 #clock-cells = <1>; 410 clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>; 411 clock-indices = <IMX_LPCG_CLK_0>; 412 clock-output-names = "mclkout0_lpcg_clk"; 413 power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; 414 }; 415 416 mclkout1_lpcg: clock-controller@59d60000 { 417 compatible = "fsl,imx8qxp-lpcg"; 418 reg = <0x59d60000 0x10000>; 419 #clock-cells = <1>; 420 clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>; 421 clock-indices = <IMX_LPCG_CLK_0>; 422 clock-output-names = "mclkout1_lpcg_clk"; 423 power-domains = <&pd IMX_SC_R_MCLK_OUT_1>; 424 }; 425 426 acm: acm@59e00000 { 427 compatible = "fsl,imx8qxp-acm"; 428 reg = <0x59e00000 0x1d0000>; 429 #clock-cells = <1>; 430 power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, 431 <&pd IMX_SC_R_AUDIO_CLK_1>, 432 <&pd IMX_SC_R_MCLK_OUT_0>, 433 <&pd IMX_SC_R_MCLK_OUT_1>, 434 <&pd IMX_SC_R_AUDIO_PLL_0>, 435 <&pd IMX_SC_R_AUDIO_PLL_1>, 436 <&pd IMX_SC_R_ASRC_0>, 437 <&pd IMX_SC_R_ASRC_1>, 438 <&pd IMX_SC_R_ESAI_0>, 439 <&pd IMX_SC_R_SAI_0>, 440 <&pd IMX_SC_R_SAI_1>, 441 <&pd IMX_SC_R_SAI_2>, 442 <&pd IMX_SC_R_SAI_3>, 443 <&pd IMX_SC_R_SAI_4>, 444 <&pd IMX_SC_R_SAI_5>, 445 <&pd IMX_SC_R_SPDIF_0>, 446 <&pd IMX_SC_R_MQS_0>; 447 clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, 448 <&aud_rec1_lpcg IMX_LPCG_CLK_0>, 449 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 450 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 451 <&clk_ext_aud_mclk0>, 452 <&clk_ext_aud_mclk1>, 453 <&clk_esai0_rx_clk>, 454 <&clk_esai0_rx_hf_clk>, 455 <&clk_esai0_tx_clk>, 456 <&clk_esai0_tx_hf_clk>, 457 <&clk_spdif0_rx>, 458 <&clk_sai0_rx_bclk>, 459 <&clk_sai0_tx_bclk>, 460 <&clk_sai1_rx_bclk>, 461 <&clk_sai1_tx_bclk>, 462 <&clk_sai2_rx_bclk>, 463 <&clk_sai3_rx_bclk>, 464 <&clk_sai4_rx_bclk>; 465 clock-names = "aud_rec_clk0_lpcg_clk", 466 "aud_rec_clk1_lpcg_clk", 467 "aud_pll_div_clk0_lpcg_clk", 468 "aud_pll_div_clk1_lpcg_clk", 469 "ext_aud_mclk0", 470 "ext_aud_mclk1", 471 "esai0_rx_clk", 472 "esai0_rx_hf_clk", 473 "esai0_tx_clk", 474 "esai0_tx_hf_clk", 475 "spdif0_rx", 476 "sai0_rx_bclk", 477 "sai0_tx_bclk", 478 "sai1_rx_bclk", 479 "sai1_tx_bclk", 480 "sai2_rx_bclk", 481 "sai3_rx_bclk", 482 "sai4_rx_bclk"; 483 }; 484}; 485