1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-lpcg.h> 8#include <dt-bindings/firmware/imx/rsrc.h> 9 10audio_ipg_clk: clock-audio-ipg { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <120000000>; 14 clock-output-names = "audio_ipg_clk"; 15}; 16 17audio_subsys: bus@59000000 { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x59000000 0x0 0x59000000 0x1000000>; 22 23 edma0: dma-controller@591f0000 { 24 compatible = "fsl,imx8qm-edma"; 25 reg = <0x591f0000 0x190000>; 26 #dma-cells = <3>; 27 shared-interrupt; 28 dma-channels = <24>; 29 dma-channel-mask = <0x5c0c00>; 30 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */ 31 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 32 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 33 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 34 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 35 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 36 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */ 37 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */ 38 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */ 39 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */ 40 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */ 41 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */ 42 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */ 43 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */ 44 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */ 45 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */ 46 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */ 47 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */ 48 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */ 49 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */ 50 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */ 51 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */ 52 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */ 53 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */ 54 power-domains = <&pd IMX_SC_R_DMA_0_CH0>, 55 <&pd IMX_SC_R_DMA_0_CH1>, 56 <&pd IMX_SC_R_DMA_0_CH2>, 57 <&pd IMX_SC_R_DMA_0_CH3>, 58 <&pd IMX_SC_R_DMA_0_CH4>, 59 <&pd IMX_SC_R_DMA_0_CH5>, 60 <&pd IMX_SC_R_DMA_0_CH6>, 61 <&pd IMX_SC_R_DMA_0_CH7>, 62 <&pd IMX_SC_R_DMA_0_CH8>, 63 <&pd IMX_SC_R_DMA_0_CH9>, 64 <&pd IMX_SC_R_DMA_0_CH10>, 65 <&pd IMX_SC_R_DMA_0_CH11>, 66 <&pd IMX_SC_R_DMA_0_CH12>, 67 <&pd IMX_SC_R_DMA_0_CH13>, 68 <&pd IMX_SC_R_DMA_0_CH14>, 69 <&pd IMX_SC_R_DMA_0_CH15>, 70 <&pd IMX_SC_R_DMA_0_CH16>, 71 <&pd IMX_SC_R_DMA_0_CH17>, 72 <&pd IMX_SC_R_DMA_0_CH18>, 73 <&pd IMX_SC_R_DMA_0_CH19>, 74 <&pd IMX_SC_R_DMA_0_CH20>, 75 <&pd IMX_SC_R_DMA_0_CH21>, 76 <&pd IMX_SC_R_DMA_0_CH22>, 77 <&pd IMX_SC_R_DMA_0_CH23>; 78 }; 79 80 dsp_lpcg: clock-controller@59580000 { 81 compatible = "fsl,imx8qxp-lpcg"; 82 reg = <0x59580000 0x10000>; 83 #clock-cells = <1>; 84 clocks = <&audio_ipg_clk>, 85 <&audio_ipg_clk>, 86 <&audio_ipg_clk>; 87 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 88 <IMX_LPCG_CLK_7>; 89 clock-output-names = "dsp_lpcg_adb_clk", 90 "dsp_lpcg_ipg_clk", 91 "dsp_lpcg_core_clk"; 92 power-domains = <&pd IMX_SC_R_DSP>; 93 }; 94 95 dsp_ram_lpcg: clock-controller@59590000 { 96 compatible = "fsl,imx8qxp-lpcg"; 97 reg = <0x59590000 0x10000>; 98 #clock-cells = <1>; 99 clocks = <&audio_ipg_clk>; 100 clock-indices = <IMX_LPCG_CLK_4>; 101 clock-output-names = "dsp_ram_lpcg_ipg_clk"; 102 power-domains = <&pd IMX_SC_R_DSP_RAM>; 103 }; 104 105 dsp: dsp@596e8000 { 106 compatible = "fsl,imx8qxp-dsp"; 107 reg = <0x596e8000 0x88000>; 108 clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, 109 <&dsp_ram_lpcg IMX_LPCG_CLK_4>, 110 <&dsp_lpcg IMX_LPCG_CLK_7>; 111 clock-names = "ipg", "ocram", "core"; 112 power-domains = <&pd IMX_SC_R_MU_13A>, 113 <&pd IMX_SC_R_MU_13B>, 114 <&pd IMX_SC_R_DSP>, 115 <&pd IMX_SC_R_DSP_RAM>; 116 mbox-names = "txdb0", "txdb1", 117 "rxdb0", "rxdb1"; 118 mboxes = <&lsio_mu13 2 0>, 119 <&lsio_mu13 2 1>, 120 <&lsio_mu13 3 0>, 121 <&lsio_mu13 3 1>; 122 memory-region = <&dsp_reserved>; 123 status = "disabled"; 124 }; 125 126 edma1: dma-controller@599f0000 { 127 compatible = "fsl,imx8qm-edma"; 128 reg = <0x599f0000 0xc0000>; 129 #dma-cells = <3>; 130 shared-interrupt; 131 dma-channels = <11>; 132 dma-channel-mask = <0xc0>; 133 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */ 134 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 135 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 136 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 137 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 138 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 139 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */ 140 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */ 141 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ 142 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ 144 power-domains = <&pd IMX_SC_R_DMA_1_CH0>, 145 <&pd IMX_SC_R_DMA_1_CH1>, 146 <&pd IMX_SC_R_DMA_1_CH2>, 147 <&pd IMX_SC_R_DMA_1_CH3>, 148 <&pd IMX_SC_R_DMA_1_CH4>, 149 <&pd IMX_SC_R_DMA_1_CH5>, 150 <&pd IMX_SC_R_DMA_1_CH6>, 151 <&pd IMX_SC_R_DMA_1_CH7>, 152 <&pd IMX_SC_R_DMA_1_CH8>, 153 <&pd IMX_SC_R_DMA_1_CH9>, 154 <&pd IMX_SC_R_DMA_1_CH10>; 155 }; 156}; 157