1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2018-2019 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7#include <dt-bindings/clock/imx8-clock.h> 8#include <dt-bindings/clock/imx8-lpcg.h> 9#include <dt-bindings/dma/fsl-edma.h> 10#include <dt-bindings/firmware/imx/rsrc.h> 11 12audio_ipg_clk: clock-audio-ipg { 13 compatible = "fixed-clock"; 14 #clock-cells = <0>; 15 clock-frequency = <120000000>; 16 clock-output-names = "audio_ipg_clk"; 17}; 18 19clk_ext_aud_mclk0: clock-ext-aud-mclk0 { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <0>; 23 clock-output-names = "ext_aud_mclk0"; 24}; 25 26clk_ext_aud_mclk1: clock-ext-aud-mclk1 { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <0>; 30 clock-output-names = "ext_aud_mclk1"; 31}; 32 33clk_esai0_rx_clk: clock-esai0-rx { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <0>; 37 clock-output-names = "esai0_rx_clk"; 38}; 39 40clk_esai0_rx_hf_clk: clock-esai0-rx-hf { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <0>; 44 clock-output-names = "esai0_rx_hf_clk"; 45}; 46 47clk_esai0_tx_clk: clock-esai0-tx { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <0>; 51 clock-output-names = "esai0_tx_clk"; 52}; 53 54clk_esai0_tx_hf_clk: clock-esai0-tx-hf { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 clock-frequency = <0>; 58 clock-output-names = "esai0_tx_hf_clk"; 59}; 60 61clk_spdif0_rx: clock-spdif0-rx { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <0>; 65 clock-output-names = "spdif0_rx"; 66}; 67 68clk_sai0_rx_bclk: clock-sai0-rx-bclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <0>; 72 clock-output-names = "sai0_rx_bclk"; 73}; 74 75clk_sai0_tx_bclk: clock-sai0-tx-bclk { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <0>; 79 clock-output-names = "sai0_tx_bclk"; 80}; 81 82clk_sai1_rx_bclk: clock-sai1-rx-bclk { 83 compatible = "fixed-clock"; 84 #clock-cells = <0>; 85 clock-frequency = <0>; 86 clock-output-names = "sai1_rx_bclk"; 87}; 88 89clk_sai1_tx_bclk: clock-sai1-tx-bclk { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 clock-output-names = "sai1_tx_bclk"; 94}; 95 96clk_sai2_rx_bclk: clock-sai2-rx-bclk { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <0>; 100 clock-output-names = "sai2_rx_bclk"; 101}; 102 103clk_sai3_rx_bclk: clock-sai3-rx-bclk { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <0>; 107 clock-output-names = "sai3_rx_bclk"; 108}; 109 110clk_sai4_rx_bclk: clock-sai4-rx-bclk { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <0>; 114 clock-output-names = "sai4_rx_bclk"; 115}; 116 117audio_subsys: bus@59000000 { 118 compatible = "simple-bus"; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges = <0x59000000 0x0 0x59000000 0x1000000>; 122 123 asrc0: asrc@59000000 { 124 compatible = "fsl,imx8qm-asrc"; 125 reg = <0x59000000 0x10000>; 126 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, 128 <&asrc0_lpcg IMX_LPCG_CLK_0>, 129 <&aud_pll_div0_lpcg IMX_LPCG_CLK_4>, 130 <&aud_pll_div1_lpcg IMX_LPCG_CLK_4>, 131 <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, 132 <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, 133 <&clk_dummy>, 134 <&clk_dummy>, 135 <&clk_dummy>, 136 <&clk_dummy>, 137 <&clk_dummy>, 138 <&clk_dummy>, 139 <&clk_dummy>, 140 <&clk_dummy>, 141 <&clk_dummy>, 142 <&clk_dummy>, 143 <&clk_dummy>, 144 <&clk_dummy>, 145 <&clk_dummy>; 146 clock-names = "mem", "ipg", 147 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 148 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 149 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 150 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 151 "spba"; 152 dmas = <&edma0 0 0 0>, 153 <&edma0 1 0 0>, 154 <&edma0 2 0 0>, 155 <&edma0 3 0 FSL_EDMA_RX>, 156 <&edma0 4 0 FSL_EDMA_RX>, 157 <&edma0 5 0 FSL_EDMA_RX>; 158 /* tx* is output channel of asrc, it is rx channel for eDMA */ 159 dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; 160 fsl,asrc-rate = <8000>; 161 fsl,asrc-width = <16>; 162 fsl,asrc-clk-map = <0>; 163 power-domains = <&pd IMX_SC_R_ASRC_0>; 164 status = "disabled"; 165 }; 166 167 esai0: esai@59010000 { 168 compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; 169 reg = <0x59010000 0x10000>; 170 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&esai0_lpcg IMX_LPCG_CLK_4>, 172 <&esai0_lpcg IMX_LPCG_CLK_0>, 173 <&esai0_lpcg IMX_LPCG_CLK_4>, 174 <&clk_dummy>; 175 clock-names = "core", "extal", "fsys", "spba"; 176 dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>; 177 dma-names = "rx", "tx"; 178 power-domains = <&pd IMX_SC_R_ESAI_0>; 179 status = "disabled"; 180 }; 181 182 spdif0: spdif@59020000 { 183 compatible = "fsl,imx8qm-spdif"; 184 reg = <0x59020000 0x10000>; 185 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ 186 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ 187 clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */ 188 <&clk_dummy>, /* rxtx0 */ 189 <&spdif0_lpcg IMX_LPCG_CLK_0>, /* rxtx1 */ 190 <&clk_dummy>, /* rxtx2 */ 191 <&clk_dummy>, /* rxtx3 */ 192 <&clk_dummy>, /* rxtx4 */ 193 <&audio_ipg_clk>, /* rxtx5 */ 194 <&clk_dummy>, /* rxtx6 */ 195 <&clk_dummy>, /* rxtx7 */ 196 <&clk_dummy>; /* spba */ 197 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", 198 "rxtx5", "rxtx6", "rxtx7", "spba"; 199 dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, 200 <&edma0 9 0 FSL_EDMA_MULTI_FIFO>; 201 dma-names = "rx", "tx"; 202 power-domains = <&pd IMX_SC_R_SPDIF_0>; 203 status = "disabled"; 204 }; 205 206 sai0: sai@59040000 { 207 compatible = "fsl,imx8qm-sai"; 208 reg = <0x59040000 0x10000>; 209 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&sai0_lpcg IMX_LPCG_CLK_4>, 211 <&clk_dummy>, 212 <&sai0_lpcg IMX_LPCG_CLK_0>, 213 <&clk_dummy>, 214 <&clk_dummy>; 215 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 216 dma-names = "rx", "tx"; 217 dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; 218 power-domains = <&pd IMX_SC_R_SAI_0>; 219 status = "disabled"; 220 }; 221 222 sai1: sai@59050000 { 223 compatible = "fsl,imx8qm-sai"; 224 reg = <0x59050000 0x10000>; 225 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&sai1_lpcg IMX_LPCG_CLK_4>, 227 <&clk_dummy>, 228 <&sai1_lpcg IMX_LPCG_CLK_0>, 229 <&clk_dummy>, 230 <&clk_dummy>; 231 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 232 dma-names = "rx", "tx"; 233 dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; 234 power-domains = <&pd IMX_SC_R_SAI_1>; 235 status = "disabled"; 236 }; 237 238 sai2: sai@59060000 { 239 compatible = "fsl,imx8qm-sai"; 240 reg = <0x59060000 0x10000>; 241 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 242 clocks = <&sai2_lpcg IMX_LPCG_CLK_4>, 243 <&clk_dummy>, 244 <&sai2_lpcg IMX_LPCG_CLK_0>, 245 <&clk_dummy>, 246 <&clk_dummy>; 247 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 248 dma-names = "rx"; 249 dmas = <&edma0 16 0 1>; 250 power-domains = <&pd IMX_SC_R_SAI_2>; 251 status = "disabled"; 252 }; 253 254 sai3: sai@59070000 { 255 compatible = "fsl,imx8qm-sai"; 256 reg = <0x59070000 0x10000>; 257 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&sai3_lpcg IMX_LPCG_CLK_4>, 259 <&clk_dummy>, 260 <&sai3_lpcg IMX_LPCG_CLK_0>, 261 <&clk_dummy>, 262 <&clk_dummy>; 263 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 264 dma-names = "rx"; 265 dmas = <&edma0 17 0 1>; 266 power-domains = <&pd IMX_SC_R_SAI_3>; 267 status = "disabled"; 268 }; 269 270 edma0: dma-controller@591f0000 { 271 compatible = "fsl,imx8qm-edma"; 272 reg = <0x591f0000 0x190000>; 273 #dma-cells = <3>; 274 dma-channels = <24>; 275 dma-channel-mask = <0x5c0c00>; 276 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */ 277 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 278 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 279 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 280 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 281 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 282 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */ 283 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */ 284 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */ 285 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */ 286 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */ 287 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */ 288 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */ 289 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */ 290 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */ 291 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */ 292 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */ 293 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */ 294 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */ 295 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */ 296 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */ 297 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */ 298 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */ 299 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */ 300 power-domains = <&pd IMX_SC_R_DMA_0_CH0>, 301 <&pd IMX_SC_R_DMA_0_CH1>, 302 <&pd IMX_SC_R_DMA_0_CH2>, 303 <&pd IMX_SC_R_DMA_0_CH3>, 304 <&pd IMX_SC_R_DMA_0_CH4>, 305 <&pd IMX_SC_R_DMA_0_CH5>, 306 <&pd IMX_SC_R_DMA_0_CH6>, 307 <&pd IMX_SC_R_DMA_0_CH7>, 308 <&pd IMX_SC_R_DMA_0_CH8>, 309 <&pd IMX_SC_R_DMA_0_CH9>, 310 <&pd IMX_SC_R_DMA_0_CH10>, 311 <&pd IMX_SC_R_DMA_0_CH11>, 312 <&pd IMX_SC_R_DMA_0_CH12>, 313 <&pd IMX_SC_R_DMA_0_CH13>, 314 <&pd IMX_SC_R_DMA_0_CH14>, 315 <&pd IMX_SC_R_DMA_0_CH15>, 316 <&pd IMX_SC_R_DMA_0_CH16>, 317 <&pd IMX_SC_R_DMA_0_CH17>, 318 <&pd IMX_SC_R_DMA_0_CH18>, 319 <&pd IMX_SC_R_DMA_0_CH19>, 320 <&pd IMX_SC_R_DMA_0_CH20>, 321 <&pd IMX_SC_R_DMA_0_CH21>, 322 <&pd IMX_SC_R_DMA_0_CH22>, 323 <&pd IMX_SC_R_DMA_0_CH23>; 324 }; 325 326 asrc0_lpcg: clock-controller@59400000 { 327 compatible = "fsl,imx8qxp-lpcg"; 328 reg = <0x59400000 0x10000>; 329 #clock-cells = <1>; 330 clocks = <&audio_ipg_clk>; 331 clock-indices = <IMX_LPCG_CLK_4>; 332 clock-output-names = "asrc0_lpcg_ipg_clk"; 333 power-domains = <&pd IMX_SC_R_ASRC_0>; 334 }; 335 336 esai0_lpcg: clock-controller@59410000 { 337 compatible = "fsl,imx8qxp-lpcg"; 338 reg = <0x59410000 0x10000>; 339 #clock-cells = <1>; 340 clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, 341 <&audio_ipg_clk>; 342 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 343 clock-output-names = "esai0_lpcg_extal_clk", 344 "esai0_lpcg_ipg_clk"; 345 power-domains = <&pd IMX_SC_R_ESAI_0>; 346 }; 347 348 spdif0_lpcg: clock-controller@59420000 { 349 compatible = "fsl,imx8qxp-lpcg"; 350 reg = <0x59420000 0x10000>; 351 #clock-cells = <1>; 352 clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, 353 <&audio_ipg_clk>; 354 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 355 clock-output-names = "spdif0_lpcg_tx_clk", 356 "spdif0_lpcg_gclkw"; 357 power-domains = <&pd IMX_SC_R_SPDIF_0>; 358 }; 359 360 sai0_lpcg: clock-controller@59440000 { 361 compatible = "fsl,imx8qxp-lpcg"; 362 reg = <0x59440000 0x10000>; 363 #clock-cells = <1>; 364 clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>, 365 <&audio_ipg_clk>; 366 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 367 clock-output-names = "sai0_lpcg_mclk", 368 "sai0_lpcg_ipg_clk"; 369 power-domains = <&pd IMX_SC_R_SAI_0>; 370 }; 371 372 sai1_lpcg: clock-controller@59450000 { 373 compatible = "fsl,imx8qxp-lpcg"; 374 reg = <0x59450000 0x10000>; 375 #clock-cells = <1>; 376 clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>, 377 <&audio_ipg_clk>; 378 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 379 clock-output-names = "sai1_lpcg_mclk", 380 "sai1_lpcg_ipg_clk"; 381 power-domains = <&pd IMX_SC_R_SAI_1>; 382 }; 383 384 sai2_lpcg: clock-controller@59460000 { 385 compatible = "fsl,imx8qxp-lpcg"; 386 reg = <0x59460000 0x10000>; 387 #clock-cells = <1>; 388 clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>, 389 <&audio_ipg_clk>; 390 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 391 clock-output-names = "sai2_lpcg_mclk", 392 "sai2_lpcg_ipg_clk"; 393 power-domains = <&pd IMX_SC_R_SAI_2>; 394 }; 395 396 sai3_lpcg: clock-controller@59470000 { 397 compatible = "fsl,imx8qxp-lpcg"; 398 reg = <0x59470000 0x10000>; 399 #clock-cells = <1>; 400 clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>, 401 <&audio_ipg_clk>; 402 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 403 clock-output-names = "sai3_lpcg_mclk", 404 "sai3_lpcg_ipg_clk"; 405 power-domains = <&pd IMX_SC_R_SAI_3>; 406 }; 407 408 dsp_lpcg: clock-controller@59580000 { 409 compatible = "fsl,imx8qxp-lpcg"; 410 reg = <0x59580000 0x10000>; 411 #clock-cells = <1>; 412 clocks = <&audio_ipg_clk>, 413 <&audio_ipg_clk>, 414 <&audio_ipg_clk>; 415 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, 416 <IMX_LPCG_CLK_7>; 417 clock-output-names = "dsp_lpcg_adb_clk", 418 "dsp_lpcg_ipg_clk", 419 "dsp_lpcg_core_clk"; 420 power-domains = <&pd IMX_SC_R_DSP>; 421 }; 422 423 dsp_ram_lpcg: clock-controller@59590000 { 424 compatible = "fsl,imx8qxp-lpcg"; 425 reg = <0x59590000 0x10000>; 426 #clock-cells = <1>; 427 clocks = <&audio_ipg_clk>; 428 clock-indices = <IMX_LPCG_CLK_4>; 429 clock-output-names = "dsp_ram_lpcg_ipg_clk"; 430 power-domains = <&pd IMX_SC_R_DSP_RAM>; 431 }; 432 433 dsp: dsp@596e8000 { 434 compatible = "fsl,imx8qxp-hifi4"; 435 reg = <0x596e8000 0x88000>; 436 clocks = <&dsp_lpcg IMX_LPCG_CLK_5>, 437 <&dsp_ram_lpcg IMX_LPCG_CLK_4>, 438 <&dsp_lpcg IMX_LPCG_CLK_7>; 439 clock-names = "ipg", "ocram", "core"; 440 power-domains = <&pd IMX_SC_R_MU_13B>, 441 <&pd IMX_SC_R_MU_2A>; 442 mbox-names = "tx", "rx", "rxdb"; 443 mboxes = <&lsio_mu13 0 0>, 444 <&lsio_mu13 1 0>, 445 <&lsio_mu13 3 0>; 446 firmware-name = "imx/dsp/hifi4.bin"; 447 status = "disabled"; 448 }; 449 450 asrc1: asrc@59800000 { 451 compatible = "fsl,imx8qm-asrc"; 452 reg = <0x59800000 0x10000>; 453 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&asrc1_lpcg IMX_LPCG_CLK_4>, 455 <&asrc1_lpcg IMX_LPCG_CLK_4>, 456 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 457 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 458 <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, 459 <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, 460 <&clk_dummy>, 461 <&clk_dummy>, 462 <&clk_dummy>, 463 <&clk_dummy>, 464 <&clk_dummy>, 465 <&clk_dummy>, 466 <&clk_dummy>, 467 <&clk_dummy>, 468 <&clk_dummy>, 469 <&clk_dummy>, 470 <&clk_dummy>, 471 <&clk_dummy>, 472 <&clk_dummy>; 473 clock-names = "mem", "ipg", 474 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 475 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 476 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 477 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 478 "spba"; 479 dmas = <&edma1 0 0 0>, 480 <&edma1 1 0 0>, 481 <&edma1 2 0 0>, 482 <&edma1 3 0 FSL_EDMA_RX>, 483 <&edma1 4 0 FSL_EDMA_RX>, 484 <&edma1 5 0 FSL_EDMA_RX>; 485 /* tx* is output channel of asrc, it is rx channel for eDMA */ 486 dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; 487 fsl,asrc-rate = <8000>; 488 fsl,asrc-width = <16>; 489 fsl,asrc-clk-map = <1>; 490 power-domains = <&pd IMX_SC_R_ASRC_1>; 491 status = "disabled"; 492 }; 493 494 sai4: sai@59820000 { 495 compatible = "fsl,imx8qm-sai"; 496 reg = <0x59820000 0x10000>; 497 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&sai4_lpcg IMX_LPCG_CLK_4>, 499 <&clk_dummy>, 500 <&sai4_lpcg IMX_LPCG_CLK_0>, 501 <&clk_dummy>, 502 <&clk_dummy>; 503 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 504 dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>; 505 dma-names = "rx", "tx"; 506 power-domains = <&pd IMX_SC_R_SAI_4>; 507 status = "disabled"; 508 }; 509 510 sai5: sai@59830000 { 511 compatible = "fsl,imx8qm-sai"; 512 reg = <0x59830000 0x10000>; 513 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&sai5_lpcg IMX_LPCG_CLK_4>, 515 <&clk_dummy>, 516 <&sai5_lpcg IMX_LPCG_CLK_0>, 517 <&clk_dummy>, 518 <&clk_dummy>; 519 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 520 dmas = <&edma1 10 0 0>; 521 dma-names = "tx"; 522 power-domains = <&pd IMX_SC_R_SAI_5>; 523 status = "disabled"; 524 }; 525 526 amix: amix@59840000 { 527 compatible = "fsl,imx8qm-audmix"; 528 reg = <0x59840000 0x10000>; 529 clocks = <&amix_lpcg IMX_LPCG_CLK_0>; 530 clock-names = "ipg"; 531 power-domains = <&pd IMX_SC_R_AMIX>; 532 dais = <&sai4>, <&sai5>; 533 status = "disabled"; 534 }; 535 536 mqs: mqs@59850000 { 537 compatible = "fsl,imx8qm-mqs"; 538 reg = <0x59850000 0x10000>; 539 clocks = <&mqs0_lpcg IMX_LPCG_CLK_4>, <&mqs0_lpcg IMX_LPCG_CLK_0>; 540 clock-names = "mclk", "core"; 541 power-domains = <&pd IMX_SC_R_MQS_0>; 542 status = "disabled"; 543 }; 544 545 edma1: dma-controller@599f0000 { 546 compatible = "fsl,imx8qm-edma"; 547 reg = <0x599f0000 0xc0000>; 548 #dma-cells = <3>; 549 dma-channels = <11>; 550 dma-channel-mask = <0xc0>; 551 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */ 552 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ 553 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ 554 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ 555 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ 556 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ 557 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */ 558 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */ 559 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ 560 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ 562 power-domains = <&pd IMX_SC_R_DMA_1_CH0>, 563 <&pd IMX_SC_R_DMA_1_CH1>, 564 <&pd IMX_SC_R_DMA_1_CH2>, 565 <&pd IMX_SC_R_DMA_1_CH3>, 566 <&pd IMX_SC_R_DMA_1_CH4>, 567 <&pd IMX_SC_R_DMA_1_CH5>, 568 <&pd IMX_SC_R_DMA_1_CH6>, 569 <&pd IMX_SC_R_DMA_1_CH7>, 570 <&pd IMX_SC_R_DMA_1_CH8>, 571 <&pd IMX_SC_R_DMA_1_CH9>, 572 <&pd IMX_SC_R_DMA_1_CH10>; 573 }; 574 575 aud_rec0_lpcg: clock-controller@59d00000 { 576 compatible = "fsl,imx8qxp-lpcg"; 577 reg = <0x59d00000 0x10000>; 578 #clock-cells = <1>; 579 clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>; 580 clock-indices = <IMX_LPCG_CLK_0>; 581 clock-output-names = "aud_rec_clk0_lpcg_clk"; 582 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; 583 }; 584 585 aud_rec1_lpcg: clock-controller@59d10000 { 586 compatible = "fsl,imx8qxp-lpcg"; 587 reg = <0x59d10000 0x10000>; 588 #clock-cells = <1>; 589 clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>; 590 clock-indices = <IMX_LPCG_CLK_0>; 591 clock-output-names = "aud_rec_clk1_lpcg_clk"; 592 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; 593 }; 594 595 aud_pll_div0_lpcg: clock-controller@59d20000 { 596 compatible = "fsl,imx8qxp-lpcg"; 597 reg = <0x59d20000 0x10000>; 598 #clock-cells = <1>; 599 clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>; 600 clock-indices = <IMX_LPCG_CLK_0>; 601 clock-output-names = "aud_pll_div_clk0_lpcg_clk"; 602 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>; 603 }; 604 605 aud_pll_div1_lpcg: clock-controller@59d30000 { 606 compatible = "fsl,imx8qxp-lpcg"; 607 reg = <0x59d30000 0x10000>; 608 #clock-cells = <1>; 609 clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>; 610 clock-indices = <IMX_LPCG_CLK_0>; 611 clock-output-names = "aud_pll_div_clk1_lpcg_clk"; 612 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>; 613 }; 614 615 mclkout0_lpcg: clock-controller@59d50000 { 616 compatible = "fsl,imx8qxp-lpcg"; 617 reg = <0x59d50000 0x10000>; 618 #clock-cells = <1>; 619 clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>; 620 clock-indices = <IMX_LPCG_CLK_0>; 621 clock-output-names = "mclkout0_lpcg_clk"; 622 power-domains = <&pd IMX_SC_R_MCLK_OUT_0>; 623 }; 624 625 mclkout1_lpcg: clock-controller@59d60000 { 626 compatible = "fsl,imx8qxp-lpcg"; 627 reg = <0x59d60000 0x10000>; 628 #clock-cells = <1>; 629 clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>; 630 clock-indices = <IMX_LPCG_CLK_0>; 631 clock-output-names = "mclkout1_lpcg_clk"; 632 power-domains = <&pd IMX_SC_R_MCLK_OUT_1>; 633 }; 634 635 acm: acm@59e00000 { 636 compatible = "fsl,imx8qxp-acm"; 637 reg = <0x59e00000 0x1d0000>; 638 #clock-cells = <1>; 639 power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, 640 <&pd IMX_SC_R_AUDIO_CLK_1>, 641 <&pd IMX_SC_R_MCLK_OUT_0>, 642 <&pd IMX_SC_R_MCLK_OUT_1>, 643 <&pd IMX_SC_R_AUDIO_PLL_0>, 644 <&pd IMX_SC_R_AUDIO_PLL_1>, 645 <&pd IMX_SC_R_ASRC_0>, 646 <&pd IMX_SC_R_ASRC_1>, 647 <&pd IMX_SC_R_ESAI_0>, 648 <&pd IMX_SC_R_SAI_0>, 649 <&pd IMX_SC_R_SAI_1>, 650 <&pd IMX_SC_R_SAI_2>, 651 <&pd IMX_SC_R_SAI_3>, 652 <&pd IMX_SC_R_SAI_4>, 653 <&pd IMX_SC_R_SAI_5>, 654 <&pd IMX_SC_R_SPDIF_0>, 655 <&pd IMX_SC_R_MQS_0>; 656 clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, 657 <&aud_rec1_lpcg IMX_LPCG_CLK_0>, 658 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 659 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 660 <&clk_ext_aud_mclk0>, 661 <&clk_ext_aud_mclk1>, 662 <&clk_esai0_rx_clk>, 663 <&clk_esai0_rx_hf_clk>, 664 <&clk_esai0_tx_clk>, 665 <&clk_esai0_tx_hf_clk>, 666 <&clk_spdif0_rx>, 667 <&clk_sai0_rx_bclk>, 668 <&clk_sai0_tx_bclk>, 669 <&clk_sai1_rx_bclk>, 670 <&clk_sai1_tx_bclk>, 671 <&clk_sai2_rx_bclk>, 672 <&clk_sai3_rx_bclk>, 673 <&clk_sai4_rx_bclk>; 674 clock-names = "aud_rec_clk0_lpcg_clk", 675 "aud_rec_clk1_lpcg_clk", 676 "aud_pll_div_clk0_lpcg_clk", 677 "aud_pll_div_clk1_lpcg_clk", 678 "ext_aud_mclk0", 679 "ext_aud_mclk1", 680 "esai0_rx_clk", 681 "esai0_rx_hf_clk", 682 "esai0_tx_clk", 683 "esai0_tx_hf_clk", 684 "spdif0_rx", 685 "sai0_rx_bclk", 686 "sai0_tx_bclk", 687 "sai1_rx_bclk", 688 "sai1_tx_bclk", 689 "sai2_rx_bclk", 690 "sai3_rx_bclk", 691 "sai4_rx_bclk"; 692 }; 693 694 asrc1_lpcg: clock-controller@59c00000 { 695 compatible = "fsl,imx8qxp-lpcg"; 696 reg = <0x59c00000 0x10000>; 697 #clock-cells = <1>; 698 clocks = <&audio_ipg_clk>; 699 clock-indices = <IMX_LPCG_CLK_4>; 700 clock-output-names = "asrc1_lpcg_ipg_clk"; 701 power-domains = <&pd IMX_SC_R_ASRC_1>; 702 }; 703 704 sai4_lpcg: clock-controller@59c20000 { 705 compatible = "fsl,imx8qxp-lpcg"; 706 reg = <0x59c20000 0x10000>; 707 #clock-cells = <1>; 708 clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, 709 <&audio_ipg_clk>; 710 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 711 clock-output-names = "sai4_lpcg_mclk", 712 "sai4_lpcg_ipg_clk"; 713 power-domains = <&pd IMX_SC_R_SAI_4>; 714 }; 715 716 sai5_lpcg: clock-controller@59c30000 { 717 compatible = "fsl,imx8qxp-lpcg"; 718 reg = <0x59c30000 0x10000>; 719 #clock-cells = <1>; 720 clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, 721 <&audio_ipg_clk>; 722 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 723 clock-output-names = "sai5_lpcg_mclk", 724 "sai5_lpcg_ipg_clk"; 725 power-domains = <&pd IMX_SC_R_SAI_5>; 726 }; 727 728 amix_lpcg: clock-controller@59c40000 { 729 compatible = "fsl,imx8qxp-lpcg"; 730 reg = <0x59c40000 0x10000>; 731 #clock-cells = <1>; 732 clocks = <&audio_ipg_clk>; 733 clock-indices = <IMX_LPCG_CLK_0>; 734 clock-output-names = "amix_lpcg_ipg_clk"; 735 power-domains = <&pd IMX_SC_R_AMIX>; 736 }; 737 738 mqs0_lpcg: clock-controller@59c50000 { 739 compatible = "fsl,imx8qxp-lpcg"; 740 reg = <0x59c50000 0x10000>; 741 #clock-cells = <1>; 742 clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, 743 <&audio_ipg_clk>; 744 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 745 clock-output-names = "mqs0_lpcg_mclk", 746 "mqs0_lpcg_ipg_clk"; 747 power-domains = <&pd IMX_SC_R_MQS_0>; 748 }; 749}; 750