1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/pwm/pwm.h> 7 8/ { 9 chosen { 10 stdout-path = &lpuart1; 11 }; 12 13 /* Apalis BKL1 */ 14 backlight: backlight { 15 compatible = "pwm-backlight"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_gpio_bkl_on>; 18 brightness-levels = <0 45 63 88 119 158 203 255>; 19 default-brightness-level = <4>; 20 enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */ 21 /* TODO: hook-up to Apalis BKL1_PWM */ 22 status = "disabled"; 23 }; 24 25 gpio_fan: gpio-fan { 26 compatible = "gpio-fan"; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_gpio8>; 29 gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>; 30 gpio-fan,speed-map = < 0 0 31 3000 1>; 32 }; 33 34 /* TODO: LVDS Panel */ 35 36 /* TODO: Shared PCIe/SATA Reference Clock */ 37 38 /* TODO: PCIe Wi-Fi Reference Clock */ 39 40 /* 41 * Power management bus used to control LDO1OUT of the 42 * second PMIC PF8100. This is used for controlling voltage levels of 43 * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS. 44 * 45 * IMX_SC_R_BOARD_R1 for 3.3V 46 * IMX_SC_R_BOARD_R2 for 1.8V 47 * IMX_SC_R_BOARD_R3 for 2.5V 48 * Note that for 2.5V operation the pad muxing needs to be changed, 49 * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD. 50 * 51 * those power domains are mutually exclusive. 52 */ 53 reg_ext_rgmii: regulator-ext-rgmii { 54 compatible = "regulator-fixed"; 55 power-domains = <&pd IMX_SC_R_BOARD_R1>; 56 regulator-max-microvolt = <3300000>; 57 regulator-min-microvolt = <3300000>; 58 regulator-name = "VDD_EXT_RGMII (LDO1)"; 59 60 regulator-state-mem { 61 regulator-off-in-suspend; 62 }; 63 }; 64 65 reg_module_3v3: regulator-module-3v3 { 66 compatible = "regulator-fixed"; 67 regulator-max-microvolt = <3300000>; 68 regulator-min-microvolt = <3300000>; 69 regulator-name = "+V3.3"; 70 }; 71 72 reg_module_3v3_avdd: regulator-module-3v3-avdd { 73 compatible = "regulator-fixed"; 74 regulator-max-microvolt = <3300000>; 75 regulator-min-microvolt = <3300000>; 76 regulator-name = "+V3.3_AUDIO"; 77 }; 78 79 reg_module_wifi: regulator-module-wifi { 80 compatible = "regulator-fixed"; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_wifi_pdn>; 83 gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; 84 enable-active-high; 85 regulator-always-on; 86 regulator-name = "wifi_pwrdn_fake_regulator"; 87 regulator-settling-time-us = <100>; 88 }; 89 90 reg_pcie_switch: regulator-pcie-switch { 91 compatible = "regulator-fixed"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&pinctrl_gpio7>; 94 gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>; 95 enable-active-high; 96 regulator-max-microvolt = <1800000>; 97 regulator-min-microvolt = <1800000>; 98 regulator-name = "pcie_switch"; 99 startup-delay-us = <100000>; 100 }; 101 102 reg_usb_host_vbus: regulator-usb-host-vbus { 103 compatible = "regulator-fixed"; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_usbh_en>; 106 /* Apalis USBH_EN */ 107 gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>; 108 enable-active-high; 109 regulator-always-on; 110 regulator-max-microvolt = <5000000>; 111 regulator-min-microvolt = <5000000>; 112 regulator-name = "usb-host-vbus"; 113 }; 114 115 reg_usb_hsic: regulator-usb-hsic { 116 compatible = "regulator-fixed"; 117 regulator-max-microvolt = <3000000>; 118 regulator-min-microvolt = <3000000>; 119 regulator-name = "usb-hsic-dummy"; 120 }; 121 122 reg_usb_phy: regulator-usb-hsic1 { 123 compatible = "regulator-fixed"; 124 regulator-max-microvolt = <3000000>; 125 regulator-min-microvolt = <3000000>; 126 regulator-name = "usb-phy-dummy"; 127 }; 128 129 reserved-memory { 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 decoder_boot: decoder-boot@84000000 { 135 reg = <0 0x84000000 0 0x2000000>; 136 no-map; 137 }; 138 139 encoder1_boot: encoder1-boot@86000000 { 140 reg = <0 0x86000000 0 0x200000>; 141 no-map; 142 }; 143 144 encoder2_boot: encoder2-boot@86200000 { 145 reg = <0 0x86200000 0 0x200000>; 146 no-map; 147 }; 148 149 /* 150 * reserved-memory layout 151 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 152 * Shouldn't be used at A core and Linux side. 153 * 154 */ 155 m4_reserved: m4@88000000 { 156 reg = <0 0x88000000 0 0x8000000>; 157 no-map; 158 }; 159 160 rpmsg_reserved: rpmsg@90200000 { 161 reg = <0 0x90200000 0 0x200000>; 162 no-map; 163 }; 164 165 vdevbuffer: vdevbuffer@90400000 { 166 compatible = "shared-dma-pool"; 167 reg = <0 0x90400000 0 0x100000>; 168 no-map; 169 }; 170 171 decoder_rpc: decoder-rpc@92000000 { 172 reg = <0 0x92000000 0 0x200000>; 173 no-map; 174 }; 175 176 dsp_reserved: dsp@92400000 { 177 reg = <0 0x92400000 0 0x2000000>; 178 no-map; 179 }; 180 181 encoder1_rpc: encoder1-rpc@94400000 { 182 reg = <0 0x94400000 0 0x700000>; 183 no-map; 184 }; 185 186 encoder2_rpc: encoder2-rpc@94b00000 { 187 reg = <0 0x94b00000 0 0x700000>; 188 no-map; 189 }; 190 191 /* global autoconfigured region for contiguous allocations */ 192 linux,cma { 193 compatible = "shared-dma-pool"; 194 alloc-ranges = <0 0xc0000000 0 0x3c000000>; 195 linux,cma-default; 196 reusable; 197 size = <0 0x3c000000>; 198 }; 199 }; 200 201 /* TODO: Apalis Analogue Audio */ 202 203 /* TODO: HDMI Audio */ 204 205 /* TODO: Apalis SPDIF1 */ 206 207 touchscreen: touchscreen { 208 compatible = "toradex,vf50-touchscreen"; 209 interrupt-parent = <&lsio_gpio3>; 210 interrupts = <22 IRQ_TYPE_LEVEL_LOW>; 211 pinctrl-names = "idle", "default"; 212 pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>; 213 pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>; 214 io-channels = <&adc1 2>, <&adc1 1>, 215 <&adc1 0>, <&adc1 3>; 216 vf50-ts-min-pressure = <200>; 217 xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>; 218 xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>; 219 yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>; 220 ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>; 221 /* 222 * NOTE: you must remove the pinctrl-adc1 from the adc1 223 * node below to use the touchscreen 224 */ 225 status = "disabled"; 226 }; 227 228}; 229 230&adc0 { 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_adc0>; 233}; 234 235&adc1 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_adc1>; 238}; 239 240/* TODO: Asynchronous Sample Rate Converter (ASRC) */ 241 242/* Apalis ETH1 */ 243&fec1 { 244 pinctrl-names = "default", "sleep"; 245 pinctrl-0 = <&pinctrl_fec1>; 246 pinctrl-1 = <&pinctrl_fec1_sleep>; 247 fsl,magic-packet; 248 phy-handle = <ðphy0>; 249 phy-mode = "rgmii-id"; 250 251 mdio { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 255 ethphy0: ethernet-phy@7 { 256 compatible = "ethernet-phy-ieee802.3-c22"; 257 reg = <7>; 258 interrupt-parent = <&lsio_gpio1>; 259 interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 260 micrel,led-mode = <0>; 261 reset-assert-us = <2>; 262 reset-deassert-us = <2>; 263 reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; 264 }; 265 }; 266}; 267 268/* Apalis CAN1 */ 269&flexcan1 { 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_flexcan1>; 272}; 273 274/* Apalis CAN2 */ 275&flexcan2 { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_flexcan2>; 278}; 279 280/* Apalis CAN3 (optional) */ 281&flexcan3 { 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_flexcan3>; 284}; 285 286/* TODO: Apalis HDMI1 */ 287 288/* On-module I2C */ 289&i2c1 { 290 pinctrl-names = "default"; 291 pinctrl-0 = <&pinctrl_lpi2c1>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 clock-frequency = <100000>; 295 status = "okay"; 296 297 /* TODO: Audio Codec */ 298 299 /* USB3503A */ 300 usb-hub@8 { 301 compatible = "smsc,usb3503a"; 302 reg = <0x08>; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&pinctrl_usb3503a>; 305 connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>; 306 initial-mode = <1>; 307 intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; 308 refclk-frequency = <25000000>; 309 reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>; 310 }; 311}; 312 313/* Apalis I2C1 */ 314&i2c2 { 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_lpi2c2>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 clock-frequency = <100000>; 320 321 atmel_mxt_ts: touch@4a { 322 compatible = "atmel,maxtouch"; 323 reg = <0x4a>; 324 interrupt-parent = <&lsio_gpio4>; 325 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ 326 pinctrl-names = "default"; 327 pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>; 328 reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_LOW>; /* Apalis GPIO6 */ 329 status = "disabled"; 330 }; 331 332 /* M41T0M6 real time clock on carrier board */ 333 rtc_i2c: rtc@68 { 334 compatible = "st,m41t0"; 335 reg = <0x68>; 336 status = "disabled"; 337 }; 338}; 339 340/* Apalis I2C3 (CAM) */ 341&i2c3 { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_lpi2c3>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 clock-frequency = <100000>; 347}; 348 349&jpegdec { 350 status = "okay"; 351}; 352 353&jpegenc { 354 status = "okay"; 355}; 356 357/* TODO: Apalis LVDS1 */ 358 359/* Apalis SPI1 */ 360&lpspi0 { 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_lpspi0>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>; 366}; 367 368/* Apalis SPI2 */ 369&lpspi2 { 370 pinctrl-names = "default"; 371 pinctrl-0 = <&pinctrl_lpspi2>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; 375}; 376 377/* Apalis UART3 */ 378&lpuart0 { 379 pinctrl-names = "default"; 380 pinctrl-0 = <&pinctrl_lpuart0>; 381}; 382 383/* Apalis UART1 */ 384&lpuart1 { 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_lpuart1>; 387}; 388 389/* Apalis UART4 */ 390&lpuart2 { 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pinctrl_lpuart2>; 393}; 394 395/* Apalis UART2 */ 396&lpuart3 { 397 pinctrl-names = "default"; 398 pinctrl-0 = <&pinctrl_lpuart3>; 399}; 400 401&lsio_gpio0 { 402 gpio-line-names = "MXM3_279", 403 "MXM3_277", 404 "MXM3_135", 405 "MXM3_203", 406 "MXM3_201", 407 "MXM3_275", 408 "MXM3_110", 409 "MXM3_120", 410 "MXM3_1/GPIO1", 411 "MXM3_3/GPIO2", 412 "MXM3_124", 413 "MXM3_122", 414 "MXM3_5/GPIO3", 415 "MXM3_7/GPIO4", 416 "", 417 "", 418 "MXM3_4", 419 "MXM3_211", 420 "MXM3_209", 421 "MXM3_2", 422 "MXM3_136", 423 "MXM3_134", 424 "MXM3_6", 425 "MXM3_8", 426 "MXM3_112", 427 "MXM3_118", 428 "MXM3_114", 429 "MXM3_116"; 430}; 431 432&lsio_gpio1 { 433 gpio-line-names = "", 434 "", 435 "", 436 "", 437 "MXM3_286", 438 "", 439 "MXM3_87", 440 "MXM3_99", 441 "MXM3_138", 442 "MXM3_140", 443 "MXM3_239", 444 "", 445 "MXM3_281", 446 "MXM3_283", 447 "MXM3_126", 448 "MXM3_132", 449 "", 450 "", 451 "", 452 "", 453 "MXM3_173", 454 "MXM3_175", 455 "MXM3_123"; 456 457 hdmi-ctrl-hog { 458 pinctrl-names = "default"; 459 pinctrl-0 = <&pinctrl_hdmi_ctrl>; 460 gpio-hog; 461 gpios = <30 GPIO_ACTIVE_HIGH>; 462 line-name = "CONNECTOR_IS_HDMI"; 463 /* Set signals depending on HDP device type, 0 DP, 1 HDMI */ 464 output-high; 465 }; 466}; 467 468&lsio_gpio2 { 469 gpio-line-names = "", 470 "", 471 "", 472 "", 473 "", 474 "", 475 "", 476 "MXM3_198", 477 "MXM3_35", 478 "MXM3_164", 479 "", 480 "", 481 "", 482 "", 483 "MXM3_217", 484 "MXM3_215", 485 "", 486 "", 487 "MXM3_193", 488 "MXM3_194", 489 "MXM3_37", 490 "", 491 "MXM3_271", 492 "MXM3_273", 493 "MXM3_195", 494 "MXM3_197", 495 "MXM3_177", 496 "MXM3_179", 497 "MXM3_181", 498 "MXM3_183", 499 "MXM3_185", 500 "MXM3_187"; 501 502 pcie-wifi-hog { 503 pinctrl-names = "default"; 504 pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; 505 gpio-hog; 506 gpios = <11 GPIO_ACTIVE_HIGH>; 507 line-name = "PCIE_WIFI_CLK"; 508 output-high; 509 }; 510}; 511 512&lsio_gpio3 { 513 gpio-line-names = "MXM3_191", 514 "", 515 "MXM3_221", 516 "MXM3_225", 517 "MXM3_223", 518 "MXM3_227", 519 "MXM3_200", 520 "MXM3_235", 521 "MXM3_231", 522 "MXM3_229", 523 "MXM3_233", 524 "MXM3_204", 525 "MXM3_196", 526 "", 527 "MXM3_202", 528 "", 529 "", 530 "", 531 "MXM3_305", 532 "MXM3_307", 533 "MXM3_309", 534 "MXM3_311", 535 "MXM3_315", 536 "MXM3_317", 537 "MXM3_319", 538 "MXM3_321", 539 "MXM3_15/GPIO7", 540 "MXM3_63", 541 "MXM3_17/GPIO8", 542 "MXM3_12", 543 "MXM3_14", 544 "MXM3_16"; 545}; 546 547&lsio_gpio4 { 548 gpio-line-names = "MXM3_18", 549 "MXM3_11/GPIO5", 550 "MXM3_13/GPIO6", 551 "MXM3_274", 552 "MXM3_84", 553 "MXM3_262", 554 "MXM3_96", 555 "", 556 "", 557 "", 558 "", 559 "", 560 "MXM3_190", 561 "", 562 "", 563 "", 564 "MXM3_269", 565 "MXM3_251", 566 "MXM3_253", 567 "MXM3_295", 568 "MXM3_299", 569 "MXM3_301", 570 "MXM3_297", 571 "MXM3_293", 572 "MXM3_291", 573 "MXM3_289", 574 "MXM3_287"; 575 576 /* Enable pcie root / sata ref clock unconditionally */ 577 pcie-sata-hog { 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pinctrl_pcie_sata_refclk>; 580 gpio-hog; 581 gpios = <11 GPIO_ACTIVE_HIGH>; 582 line-name = "PCIE_SATA_CLK"; 583 output-high; 584 }; 585}; 586 587&lsio_gpio5 { 588 gpio-line-names = "", 589 "", 590 "", 591 "", 592 "", 593 "", 594 "", 595 "", 596 "", 597 "", 598 "", 599 "", 600 "", 601 "", 602 "MXM3_150", 603 "MXM3_160", 604 "MXM3_162", 605 "MXM3_144", 606 "MXM3_146", 607 "MXM3_148", 608 "MXM3_152", 609 "MXM3_156", 610 "MXM3_158", 611 "MXM3_159", 612 "MXM3_184", 613 "MXM3_180", 614 "MXM3_186", 615 "MXM3_188", 616 "MXM3_176", 617 "MXM3_178"; 618}; 619 620&lsio_gpio6 { 621 gpio-line-names = "", 622 "", 623 "", 624 "", 625 "", 626 "", 627 "", 628 "", 629 "", 630 "", 631 "MXM3_261", 632 "MXM3_263", 633 "MXM3_259", 634 "MXM3_257", 635 "MXM3_255", 636 "MXM3_128", 637 "MXM3_130", 638 "MXM3_265", 639 "MXM3_249", 640 "MXM3_247", 641 "MXM3_245", 642 "MXM3_243"; 643}; 644 645/* Apalis PWM3, MXM3 pin 6 */ 646&lsio_pwm0 { 647 pinctrl-names = "default"; 648 pinctrl-0 = <&pinctrl_pwm0>; 649 #pwm-cells = <3>; 650}; 651 652/* Apalis PWM4, MXM3 pin 8 */ 653&lsio_pwm1 { 654 pinctrl-names = "default"; 655 pinctrl-0 = <&pinctrl_pwm1>; 656 #pwm-cells = <3>; 657}; 658 659/* Apalis PWM1, MXM3 pin 2 */ 660&lsio_pwm2 { 661 pinctrl-names = "default"; 662 pinctrl-0 = <&pinctrl_pwm2>; 663 #pwm-cells = <3>; 664}; 665 666/* Apalis PWM2, MXM3 pin 4 */ 667&lsio_pwm3 { 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_pwm3>; 670 #pwm-cells = <3>; 671}; 672 673/* Messaging Units */ 674&mu_m0 { 675 status = "okay"; 676}; 677 678&mu1_m0 { 679 status = "okay"; 680}; 681 682&mu2_m0 { 683 status = "okay"; 684}; 685 686/* TODO: Apalis PCIE1 */ 687 688/* TODO: On-module Wi-Fi */ 689 690/* TODO: Apalis BKL1_PWM */ 691 692/* TODO: Apalis DAP1 */ 693 694/* TODO: Analogue Audio */ 695 696/* TODO: Apalis SATA1 */ 697 698/* TODO: Apalis SPDIF1 */ 699 700/* TODO: Thermal Zones */ 701 702/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ 703 704/* TODO: Apalis USBH4 */ 705 706/* Apalis USBO1 */ 707&usbphy1 { 708 phy-3p0-supply = <®_usb_phy>; 709 status = "okay"; 710}; 711 712&usbotg1 { 713 pinctrl-names = "default"; 714 pinctrl-0 = <&pinctrl_usbotg1>; 715 adp-disable; 716 hnp-disable; 717 over-current-active-low; 718 power-active-high; 719 srp-disable; 720}; 721 722/* On-module eMMC */ 723&usdhc1 { 724 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 725 pinctrl-0 = <&pinctrl_usdhc1>; 726 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 727 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 728 bus-width = <8>; 729 non-removable; 730 status = "okay"; 731}; 732 733/* Apalis MMC1 */ 734&usdhc2 { 735 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 736 pinctrl-0 = <&pinctrl_usdhc2_4bit>, 737 <&pinctrl_usdhc2_8bit>, 738 <&pinctrl_mmc1_cd>; 739 pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, 740 <&pinctrl_usdhc2_8bit_100mhz>, 741 <&pinctrl_mmc1_cd>; 742 pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, 743 <&pinctrl_usdhc2_8bit_200mhz>, 744 <&pinctrl_mmc1_cd>; 745 pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, 746 <&pinctrl_usdhc2_8bit_sleep>, 747 <&pinctrl_mmc1_cd_sleep>; 748 bus-width = <8>; 749 cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ 750 no-1-8-v; 751}; 752 753/* Apalis SD1 */ 754&usdhc3 { 755 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 756 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; 757 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>; 758 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>; 759 bus-width = <4>; 760 cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */ 761 no-1-8-v; 762}; 763 764/* Video Processing Unit */ 765&vpu { 766 compatible = "nxp,imx8qm-vpu"; 767 status = "okay"; 768}; 769 770&vpu_core0 { 771 reg = <0x2d080000 0x10000>; 772 memory-region = <&decoder_boot>, <&decoder_rpc>; 773 status = "okay"; 774}; 775 776&vpu_core1 { 777 reg = <0x2d090000 0x10000>; 778 memory-region = <&encoder1_boot>, <&encoder1_rpc>; 779 status = "okay"; 780}; 781 782&vpu_core2 { 783 reg = <0x2d0a0000 0x10000>; 784 memory-region = <&encoder2_boot>, <&encoder2_rpc>; 785 status = "okay"; 786}; 787 788&iomuxc { 789 pinctrl-names = "default"; 790 pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, 791 <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, 792 <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>, 793 <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>, 794 <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, 795 <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, 796 <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>, 797 <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>, 798 <&pinctrl_usdhc1_gpios>; 799 800 /* Apalis AN1_ADC */ 801 pinctrl_adc0: adc0grp { 802 fsl,pins = /* Apalis AN1_ADC0 */ 803 <IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060>, 804 /* Apalis AN1_ADC1 */ 805 <IMX8QM_ADC_IN1_DMA_ADC0_IN1 0xc0000060>, 806 /* Apalis AN1_ADC2 */ 807 <IMX8QM_ADC_IN2_DMA_ADC0_IN2 0xc0000060>, 808 /* Apalis AN1_TSWIP_ADC3 */ 809 <IMX8QM_ADC_IN3_DMA_ADC0_IN3 0xc0000060>; 810 }; 811 812 /* Apalis AN1_TS */ 813 pinctrl_adc1: adc1grp { 814 fsl,pins = /* Apalis AN1_TSPX */ 815 <IMX8QM_ADC_IN4_DMA_ADC1_IN0 0xc0000060>, 816 /* Apalis AN1_TSMX */ 817 <IMX8QM_ADC_IN5_DMA_ADC1_IN1 0xc0000060>, 818 /* Apalis AN1_TSPY */ 819 <IMX8QM_ADC_IN6_DMA_ADC1_IN2 0xc0000060>, 820 /* Apalis AN1_TSMY */ 821 <IMX8QM_ADC_IN7_DMA_ADC1_IN3 0xc0000060>; 822 }; 823 824 /* Apalis CAM1 */ 825 pinctrl_cam1_gpios: cam1gpiosgrp { 826 fsl,pins = /* Apalis CAM1_D7 */ 827 <IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021>, 828 /* Apalis CAM1_D6 */ 829 <IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021>, 830 /* Apalis CAM1_D5 */ 831 <IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021>, 832 /* Apalis CAM1_D4 */ 833 <IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021>, 834 /* Apalis CAM1_D3 */ 835 <IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021>, 836 /* Apalis CAM1_D2 */ 837 <IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021>, 838 /* Apalis CAM1_D1 */ 839 <IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021>, 840 /* Apalis CAM1_D0 */ 841 <IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021>, 842 /* Apalis CAM1_PCLK */ 843 <IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021>, 844 /* Apalis CAM1_MCLK */ 845 <IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021>, 846 /* Apalis CAM1_VSYNC */ 847 <IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021>, 848 /* Apalis CAM1_HSYNC */ 849 <IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021>; 850 }; 851 852 /* Apalis DAP1 */ 853 pinctrl_dap1_gpios: dap1gpiosgrp { 854 fsl,pins = /* Apalis DAP1_MCLK */ 855 <IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021>, 856 /* Apalis DAP1_D_OUT */ 857 <IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021>, 858 /* Apalis DAP1_RESET */ 859 <IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021>, 860 /* Apalis DAP1_BIT_CLK */ 861 <IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021>, 862 /* Apalis DAP1_D_IN */ 863 <IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021>, 864 /* Apalis DAP1_SYNC */ 865 <IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021>, 866 /* On-module Wi-Fi_I2S_EN# */ 867 <IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021>; 868 }; 869 870 /* Apalis LCD1_G1+2 */ 871 pinctrl_esai0_gpios: esai0gpiosgrp { 872 fsl,pins = /* Apalis LCD1_G1 */ 873 <IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021>, 874 /* Apalis LCD1_G2 */ 875 <IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021>; 876 }; 877 878 /* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */ 879 pinctrl_fec1: fec1grp { 880 fsl,pins = /* Use pads in 3.3V mode */ 881 <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>, 882 <IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020>, 883 <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>, 884 <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020>, 885 <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020>, 886 <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020>, 887 <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020>, 888 <IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020>, 889 <IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020>, 890 <IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020>, 891 <IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020>, 892 <IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020>, 893 <IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020>, 894 <IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020>, 895 <IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020>, 896 <IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020>, 897 /* On-module ETH_RESET# */ 898 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>, 899 /* On-module ETH_INT# */ 900 <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000060>; 901 }; 902 903 pinctrl_fec1_sleep: fec1-sleepgrp { 904 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>, 905 <IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040>, 906 <IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040>, 907 <IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040>, 908 <IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040>, 909 <IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040>, 910 <IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040>, 911 <IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040>, 912 <IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040>, 913 <IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040>, 914 <IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040>, 915 <IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040>, 916 <IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040>, 917 <IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040>, 918 <IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040>, 919 <IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040>, 920 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>, 921 <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000040>; 922 }; 923 924 /* Apalis LCD1_ */ 925 pinctrl_fec2_gpios: fec2gpiosgrp { 926 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0>, 927 /* Apalis LCD1_R1 */ 928 <IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021>, 929 /* Apalis LCD1_R0 */ 930 <IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021>, 931 /* Apalis LCD1_G0 */ 932 <IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021>, 933 /* Apalis LCD1_R7 */ 934 <IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021>, 935 /* Apalis LCD1_DE */ 936 <IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021>, 937 /* Apalis LCD1_HSYNC */ 938 <IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021>, 939 /* Apalis LCD1_VSYNC */ 940 <IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021>, 941 /* Apalis LCD1_PCLK */ 942 <IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021>, 943 /* Apalis LCD1_R6 */ 944 <IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021>, 945 /* Apalis LCD1_R5 */ 946 <IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021>, 947 /* Apalis LCD1_R4 */ 948 <IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021>, 949 /* Apalis LCD1_R3 */ 950 <IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021>, 951 /* Apalis LCD1_R2 */ 952 <IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021>; 953 }; 954 955 /* Apalis CAN1 */ 956 pinctrl_flexcan1: flexcan0grp { 957 fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021>, 958 <IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021>; 959 }; 960 961 /* Apalis CAN2 */ 962 pinctrl_flexcan2: flexcan1grp { 963 fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021>, 964 <IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021>; 965 }; 966 967 /* Apalis CAN3 (optional) */ 968 pinctrl_flexcan3: flexcan2grp { 969 fsl,pins = <IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x00000021>, 970 <IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x00000021>; 971 }; 972 973 /* Apalis GPIO1 */ 974 pinctrl_gpio1: gpio1grp { 975 fsl,pins = <IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021>; 976 }; 977 978 /* Apalis GPIO2 */ 979 pinctrl_gpio2: gpio2grp { 980 fsl,pins = <IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021>; 981 }; 982 983 /* Apalis GPIO3 */ 984 pinctrl_gpio3: gpio3grp { 985 fsl,pins = <IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021>; 986 }; 987 988 /* Apalis GPIO4 */ 989 pinctrl_gpio4: gpio4grp { 990 fsl,pins = <IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021>; 991 }; 992 993 /* Apalis GPIO5 */ 994 pinctrl_gpio5: gpio5grp { 995 fsl,pins = <IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021>; 996 }; 997 998 /* Apalis GPIO6 */ 999 pinctrl_gpio6: gpio6grp { 1000 fsl,pins = <IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x00000021>; 1001 }; 1002 1003 /* Apalis GPIO7 */ 1004 pinctrl_gpio7: gpio7grp { 1005 fsl,pins = <IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 0x00000021>; 1006 }; 1007 1008 /* Apalis GPIO8 */ 1009 pinctrl_gpio8: gpio8grp { 1010 fsl,pins = <IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 0x00000021>; 1011 }; 1012 1013 /* Apalis BKL1_ON */ 1014 pinctrl_gpio_bkl_on: gpiobklongrp { 1015 fsl,pins = <IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021>; 1016 }; 1017 1018 /* Apalis WAKE1_MICO */ 1019 pinctrl_gpio_keys: gpiokeysgrp { 1020 fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 0x06700021>; 1021 }; 1022 1023 /* Apalis USBH_OC# */ 1024 pinctrl_gpio_usbh_oc_n: gpiousbhocngrp { 1025 fsl,pins = <IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x04000021>; 1026 }; 1027 1028 /* On-module HDMI_CTRL */ 1029 pinctrl_hdmi_ctrl: hdmictrlgrp { 1030 fsl,pins = <IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000061>; 1031 }; 1032 1033 /* On-module I2C */ 1034 pinctrl_lpi2c1: lpi2c1grp { 1035 fsl,pins = <IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x04000020>, 1036 <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020>; 1037 }; 1038 1039 /* Apalis I2C1 */ 1040 pinctrl_lpi2c2: lpi2c2grp { 1041 fsl,pins = <IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0x04000020>, 1042 <IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020>; 1043 }; 1044 1045 /* Apalis I2C3 (CAM) */ 1046 pinctrl_lpi2c3: lpi2c3grp { 1047 fsl,pins = <IMX8QM_SIM0_PD_DMA_I2C3_SCL 0x04000020>, 1048 <IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020>; 1049 }; 1050 1051 /* Apalis SPI1 */ 1052 pinctrl_lpspi0: lpspi0grp { 1053 fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x0600004c>, 1054 <IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x0600004c>, 1055 <IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x0600004c>, 1056 <IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x0600004c>; 1057 }; 1058 1059 /* Apalis SPI2 */ 1060 pinctrl_lpspi2: lpspi2grp { 1061 fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c>, 1062 <IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c>, 1063 <IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c>, 1064 <IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x0600004c>; 1065 }; 1066 1067 /* Apalis UART3 */ 1068 pinctrl_lpuart0: lpuart0grp { 1069 fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020>, 1070 <IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020>; 1071 }; 1072 1073 /* Apalis UART1 */ 1074 pinctrl_lpuart1: lpuart1grp { 1075 fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020>, 1076 <IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020>, 1077 <IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020>, 1078 <IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020>; 1079 }; 1080 1081 /* Apalis UART1 */ 1082 pinctrl_lpuart1ctrl: lpuart1ctrlgrp { 1083 fsl,pins = /* Apalis UART1_DTR */ 1084 <IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021>, 1085 /* Apalis UART1_DSR */ 1086 <IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021>, 1087 /* Apalis UART1_DCD */ 1088 <IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021>, 1089 /* Apalis UART1_RI */ 1090 <IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021>; 1091 }; 1092 1093 /* Apalis UART4 */ 1094 pinctrl_lpuart2: lpuart2grp { 1095 fsl,pins = <IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020>, 1096 <IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020>; 1097 }; 1098 1099 /* Apalis UART2 */ 1100 pinctrl_lpuart3: lpuart3grp { 1101 fsl,pins = <IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020>, 1102 <IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020>, 1103 <IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020>, 1104 <IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020>; 1105 }; 1106 1107 /* Apalis TS_2 */ 1108 pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp { 1109 fsl,pins = <IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021>; 1110 }; 1111 1112 /* Apalis LCD1_G6+7 */ 1113 pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp { 1114 fsl,pins = /* Apalis LCD1_G6 */ 1115 <IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021>, 1116 /* Apalis LCD1_G7 */ 1117 <IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021>; 1118 }; 1119 1120 /* Apalis TS_3 */ 1121 pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp { 1122 fsl,pins = <IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021>; 1123 }; 1124 1125 /* Apalis TS_4 */ 1126 pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp { 1127 fsl,pins = <IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021>; 1128 }; 1129 1130 /* Apalis TS_1 */ 1131 pinctrl_mlb_gpios: mlbgpiosgrp { 1132 fsl,pins = <IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 0x00000021>; 1133 }; 1134 1135 /* Apalis MMC1_CD# */ 1136 pinctrl_mmc1_cd: mmc1cdgrp { 1137 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021>; 1138 }; 1139 1140 pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp { 1141 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x04000021>; 1142 }; 1143 1144 /* On-module PCIe_Wi-Fi */ 1145 pinctrl_pcieb: pciebgrp { 1146 fsl,pins = <IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021>, 1147 <IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021>, 1148 <IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021>; 1149 }; 1150 1151 /* On-module PCIe_CLK_EN1 */ 1152 pinctrl_pcie_sata_refclk: pciesatarefclkgrp { 1153 fsl,pins = <IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021>; 1154 }; 1155 1156 /* On-module PCIe_CLK_EN2 */ 1157 pinctrl_pcie_wifi_refclk: pciewifirefclkgrp { 1158 fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 0x00000021>; 1159 }; 1160 1161 /* Apalis PWM3 */ 1162 pinctrl_pwm0: pwm0grp { 1163 fsl,pins = <IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT 0x00000020>; 1164 }; 1165 1166 /* Apalis PWM4 */ 1167 pinctrl_pwm1: pwm1grp { 1168 fsl,pins = <IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT 0x00000020>; 1169 }; 1170 1171 /* Apalis PWM1 */ 1172 pinctrl_pwm2: pwm2grp { 1173 fsl,pins = <IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT 0x00000020>; 1174 }; 1175 1176 /* Apalis PWM2 */ 1177 pinctrl_pwm3: pwm3grp { 1178 fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT 0x00000020>; 1179 }; 1180 1181 /* Apalis BKL1_PWM */ 1182 pinctrl_pwm_bkl: pwmbklgrp { 1183 fsl,pins = <IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020>; 1184 }; 1185 1186 /* Apalis LCD1_ */ 1187 pinctrl_qspi1a_gpios: qspi1agpiosgrp { 1188 fsl,pins = /* Apalis LCD1_B0 */ 1189 <IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021>, 1190 /* Apalis LCD1_B1 */ 1191 <IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021>, 1192 /* Apalis LCD1_B2 */ 1193 <IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021>, 1194 /* Apalis LCD1_B3 */ 1195 <IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021>, 1196 /* Apalis LCD1_B5 */ 1197 <IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021>, 1198 /* Apalis LCD1_B7 */ 1199 <IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021>, 1200 /* Apalis LCD1_B4 */ 1201 <IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021>, 1202 /* Apalis LCD1_B6 */ 1203 <IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021>; 1204 }; 1205 1206 /* On-module RESET_MOCI#_DRV */ 1207 pinctrl_reset_moci: resetmocigrp { 1208 fsl,pins = <IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021>; 1209 }; 1210 1211 /* On-module I2S SGTL5000 for Apalis Analogue Audio */ 1212 pinctrl_sai1: sai1grp { 1213 fsl,pins = <IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0xc600006c>, 1214 <IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0xc600004c>, 1215 <IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0xc600004c>, 1216 <IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0xc600004c>; 1217 }; 1218 1219 /* Apalis SATA1_ACT# */ 1220 pinctrl_sata1_act: sata1actgrp { 1221 fsl,pins = <IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021>; 1222 }; 1223 1224 /* Apalis SD1_CD# */ 1225 pinctrl_sd1_cd: sd1cdgrp { 1226 fsl,pins = <IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021>; 1227 }; 1228 1229 /* On-module I2S SGTL5000 SYS_MCLK */ 1230 pinctrl_sgtl5000: sgtl5000grp { 1231 fsl,pins = <IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c>; 1232 }; 1233 1234 /* Apalis LCD1_ */ 1235 pinctrl_sim0_gpios: sim0gpiosgrp { 1236 fsl,pins = /* Apalis LCD1_G5 */ 1237 <IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021>, 1238 /* Apalis LCD1_G3 */ 1239 <IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021>, 1240 /* Apalis TS_5 */ 1241 <IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 0x00000021>, 1242 /* Apalis LCD1_G4 */ 1243 <IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 0x00000021>; 1244 }; 1245 1246 /* Apalis SPDIF */ 1247 pinctrl_spdif0: spdif0grp { 1248 fsl,pins = <IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040>, 1249 <IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040>; 1250 }; 1251 1252 pinctrl_touchctrl_gpios: touchctrlgpiosgrp { 1253 fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000021>, 1254 <IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041>, 1255 <IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021>, 1256 <IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 0x00000041>; 1257 }; 1258 1259 pinctrl_touchctrl_idle: touchctrlidlegrp { 1260 fsl,pins = <IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 0x00000021>, 1261 <IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 0x00000021>, 1262 <IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021>, 1263 <IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 0x00000021>; 1264 }; 1265 1266 /* On-module USB HSIC HUB (active) */ 1267 pinctrl_usb_hsic_active: usbh1activegrp { 1268 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0x000000cf>, 1269 <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0x000000ff>; 1270 }; 1271 1272 /* On-module USB HSIC HUB (idle) */ 1273 pinctrl_usb_hsic_idle: usbh1idlegrp { 1274 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0x000000cf>, 1275 <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0x000000cf>; 1276 }; 1277 1278 /* On-module USB HSIC HUB */ 1279 pinctrl_usb3503a: usb3503agrp { 1280 fsl,pins = /* On-module HSIC_HUB_CONNECT */ 1281 <IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x00000041>, 1282 /* On-module HSIC_INT_N */ 1283 <IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021>, 1284 /* On-module HSIC_RESET_N */ 1285 <IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000041>; 1286 }; 1287 1288 /* Apalis USBH_EN */ 1289 pinctrl_usbh_en: usbhengrp { 1290 fsl,pins = <IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021>; 1291 }; 1292 1293 /* Apalis USBO1 */ 1294 pinctrl_usbotg1: usbotg1grp { 1295 fsl,pins = /* Apalis USBO1_EN */ 1296 <IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>, 1297 /* Apalis USBO1_OC# */ 1298 <IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC 0x04000021>; 1299 }; 1300 1301 /* On-module eMMC */ 1302 pinctrl_usdhc1: usdhc1grp { 1303 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 1304 <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>, 1305 <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>, 1306 <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>, 1307 <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>, 1308 <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>, 1309 <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>, 1310 <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>, 1311 <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>, 1312 <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>, 1313 <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041>, 1314 <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>; 1315 }; 1316 1317 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1318 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>, 1319 <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>, 1320 <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>, 1321 <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>, 1322 <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>, 1323 <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>, 1324 <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>, 1325 <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>, 1326 <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>, 1327 <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>, 1328 <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040>, 1329 <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020>; 1330 }; 1331 1332 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1333 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>, 1334 <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>, 1335 <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>, 1336 <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>, 1337 <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>, 1338 <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>, 1339 <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>, 1340 <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>, 1341 <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>, 1342 <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>, 1343 <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040>, 1344 <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020>; 1345 }; 1346 1347 /* Apalis TS_6 */ 1348 pinctrl_usdhc1_gpios: usdhc1gpiosgrp { 1349 fsl,pins = <IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021>; 1350 }; 1351 1352 /* Apalis MMC1 */ 1353 pinctrl_usdhc2_4bit: usdhc2grp4bitgrp { 1354 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, 1355 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>, 1356 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>, 1357 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>, 1358 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>, 1359 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>, 1360 /* On-module PMIC use */ 1361 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 1362 }; 1363 1364 pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp { 1365 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, 1366 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, 1367 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, 1368 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, 1369 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, 1370 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, 1371 /* On-module PMIC use */ 1372 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 1373 }; 1374 1375 pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp { 1376 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, 1377 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, 1378 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, 1379 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, 1380 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, 1381 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, 1382 /* On-module PMIC use */ 1383 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 1384 }; 1385 1386 pinctrl_usdhc2_8bit: usdhc2grp8bitgrp { 1387 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021>, 1388 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021>, 1389 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021>, 1390 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021>; 1391 }; 1392 1393 pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp { 1394 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020>, 1395 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020>, 1396 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020>, 1397 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020>; 1398 }; 1399 1400 pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp { 1401 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020>, 1402 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020>, 1403 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020>, 1404 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020>; 1405 }; 1406 1407 pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp { 1408 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x04000061>, 1409 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x04000061>, 1410 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x04000061>, 1411 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x04000061>, 1412 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x04000061>, 1413 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x04000061>, 1414 /* On-module PMIC use */ 1415 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 1416 }; 1417 1418 pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp { 1419 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x04000061>, 1420 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x04000061>, 1421 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x04000061>, 1422 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x04000061>; 1423 }; 1424 1425 /* Apalis SD1 */ 1426 pinctrl_usdhc3: usdhc3grp { 1427 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>, 1428 <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>, 1429 <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>, 1430 <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>, 1431 <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>, 1432 <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>, 1433 /* On-module PMIC use */ 1434 <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>; 1435 }; 1436 1437 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1438 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>, 1439 <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>, 1440 <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>, 1441 <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>, 1442 <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>, 1443 <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>, 1444 /* On-module PMIC use */ 1445 <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>; 1446 }; 1447 1448 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1449 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>, 1450 <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>, 1451 <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>, 1452 <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>, 1453 <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>, 1454 <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>, 1455 /* On-module PMIC use */ 1456 <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>; 1457 }; 1458 1459 /* On-module Wi-Fi */ 1460 pinctrl_wifi: wifigrp { 1461 fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */ 1462 <IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x06000021>, 1463 /* On-module Wi-Fi_PCIE_W_DISABLE */ 1464 <IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x06000021>; 1465 }; 1466 1467 pinctrl_wifi_pdn: wifipdngrp { 1468 fsl,pins = /* On-module Wi-Fi_POWER_DOWN */ 1469 <IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021>; 1470 }; 1471}; 1472