1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include <dt-bindings/pwm/pwm.h> 7 8/ { 9 chosen { 10 stdout-path = &lpuart1; 11 }; 12 13 /* Apalis BKL1 */ 14 backlight: backlight { 15 compatible = "pwm-backlight"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_gpio_bkl_on>; 18 brightness-levels = <0 45 63 88 119 158 203 255>; 19 default-brightness-level = <4>; 20 enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */ 21 /* TODO: hook-up to Apalis BKL1_PWM */ 22 status = "disabled"; 23 }; 24 25 gpio_fan: gpio-fan { 26 compatible = "gpio-fan"; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_gpio8>; 29 gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>; 30 gpio-fan,speed-map = < 0 0 31 3000 1>; 32 }; 33 34 /* TODO: LVDS Panel */ 35 36 /* TODO: Shared PCIe/SATA Reference Clock */ 37 38 /* TODO: PCIe Wi-Fi Reference Clock */ 39 40 /* 41 * Power management bus used to control LDO1OUT of the 42 * second PMIC PF8100. This is used for controlling voltage levels of 43 * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS. 44 * 45 * IMX_SC_R_BOARD_R1 for 3.3V 46 * IMX_SC_R_BOARD_R2 for 1.8V 47 * IMX_SC_R_BOARD_R3 for 2.5V 48 * Note that for 2.5V operation the pad muxing needs to be changed, 49 * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD. 50 * 51 * those power domains are mutually exclusive. 52 */ 53 reg_ext_rgmii: regulator-ext-rgmii { 54 compatible = "regulator-fixed"; 55 power-domains = <&pd IMX_SC_R_BOARD_R1>; 56 regulator-max-microvolt = <3300000>; 57 regulator-min-microvolt = <3300000>; 58 regulator-name = "VDD_EXT_RGMII (LDO1)"; 59 60 regulator-state-mem { 61 regulator-off-in-suspend; 62 }; 63 }; 64 65 reg_module_3v3: regulator-module-3v3 { 66 compatible = "regulator-fixed"; 67 regulator-max-microvolt = <3300000>; 68 regulator-min-microvolt = <3300000>; 69 regulator-name = "+V3.3"; 70 }; 71 72 reg_module_3v3_avdd: regulator-module-3v3-avdd { 73 compatible = "regulator-fixed"; 74 regulator-max-microvolt = <3300000>; 75 regulator-min-microvolt = <3300000>; 76 regulator-name = "+V3.3_AUDIO"; 77 }; 78 79 reg_module_wifi: regulator-module-wifi { 80 compatible = "regulator-fixed"; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_wifi_pdn>; 83 gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; 84 enable-active-high; 85 regulator-name = "wifi_pwrdn_fake_regulator"; 86 regulator-settling-time-us = <100>; 87 88 regulator-state-mem { 89 regulator-off-in-suspend; 90 }; 91 }; 92 93 reg_pcie_switch: regulator-pcie-switch { 94 compatible = "regulator-fixed"; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&pinctrl_gpio7>; 97 gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>; 98 enable-active-high; 99 regulator-max-microvolt = <1800000>; 100 regulator-min-microvolt = <1800000>; 101 regulator-name = "pcie_switch"; 102 startup-delay-us = <100000>; 103 }; 104 105 reg_usb_host_vbus: regulator-usb-host-vbus { 106 compatible = "regulator-fixed"; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_usbh_en>; 109 /* Apalis USBH_EN */ 110 gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>; 111 enable-active-high; 112 regulator-always-on; 113 regulator-max-microvolt = <5000000>; 114 regulator-min-microvolt = <5000000>; 115 regulator-name = "usb-host-vbus"; 116 }; 117 118 reg_usb_hsic: regulator-usb-hsic { 119 compatible = "regulator-fixed"; 120 regulator-max-microvolt = <3000000>; 121 regulator-min-microvolt = <3000000>; 122 regulator-name = "usb-hsic-dummy"; 123 }; 124 125 reg_usb_phy: regulator-usb-hsic1 { 126 compatible = "regulator-fixed"; 127 regulator-max-microvolt = <3000000>; 128 regulator-min-microvolt = <3000000>; 129 regulator-name = "usb-phy-dummy"; 130 }; 131 132 reserved-memory { 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 decoder_boot: decoder-boot@84000000 { 138 reg = <0 0x84000000 0 0x2000000>; 139 no-map; 140 }; 141 142 encoder1_boot: encoder1-boot@86000000 { 143 reg = <0 0x86000000 0 0x200000>; 144 no-map; 145 }; 146 147 encoder2_boot: encoder2-boot@86200000 { 148 reg = <0 0x86200000 0 0x200000>; 149 no-map; 150 }; 151 152 /* 153 * reserved-memory layout 154 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 155 * Shouldn't be used at A core and Linux side. 156 * 157 */ 158 m4_reserved: m4@88000000 { 159 reg = <0 0x88000000 0 0x8000000>; 160 no-map; 161 }; 162 163 rpmsg_reserved: rpmsg@90200000 { 164 reg = <0 0x90200000 0 0x200000>; 165 no-map; 166 }; 167 168 vdevbuffer: vdevbuffer@90400000 { 169 compatible = "shared-dma-pool"; 170 reg = <0 0x90400000 0 0x100000>; 171 no-map; 172 }; 173 174 decoder_rpc: decoder-rpc@92000000 { 175 reg = <0 0x92000000 0 0x200000>; 176 no-map; 177 }; 178 179 dsp_reserved: dsp@92400000 { 180 reg = <0 0x92400000 0 0x2000000>; 181 no-map; 182 }; 183 184 encoder1_rpc: encoder1-rpc@94400000 { 185 reg = <0 0x94400000 0 0x700000>; 186 no-map; 187 }; 188 189 encoder2_rpc: encoder2-rpc@94b00000 { 190 reg = <0 0x94b00000 0 0x700000>; 191 no-map; 192 }; 193 194 /* global autoconfigured region for contiguous allocations */ 195 linux,cma { 196 compatible = "shared-dma-pool"; 197 alloc-ranges = <0 0xc0000000 0 0x3c000000>; 198 linux,cma-default; 199 reusable; 200 size = <0 0x3c000000>; 201 }; 202 }; 203 204 /* TODO: Apalis Analogue Audio */ 205 206 /* TODO: HDMI Audio */ 207 208 /* TODO: Apalis SPDIF1 */ 209 210 touchscreen: touchscreen { 211 compatible = "toradex,vf50-touchscreen"; 212 interrupt-parent = <&lsio_gpio3>; 213 interrupts = <22 IRQ_TYPE_LEVEL_LOW>; 214 pinctrl-names = "idle", "default"; 215 pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>; 216 pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>; 217 io-channels = <&adc1 2>, <&adc1 1>, 218 <&adc1 0>, <&adc1 3>; 219 vf50-ts-min-pressure = <200>; 220 xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>; 221 xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>; 222 yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>; 223 ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>; 224 /* 225 * NOTE: you must remove the pinctrl-adc1 from the adc1 226 * node below to use the touchscreen 227 */ 228 status = "disabled"; 229 }; 230 231}; 232 233&adc0 { 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_adc0>; 236}; 237 238&adc1 { 239 pinctrl-names = "default"; 240 pinctrl-0 = <&pinctrl_adc1>; 241}; 242 243/* TODO: Asynchronous Sample Rate Converter (ASRC) */ 244 245/* Apalis ETH1 */ 246&fec1 { 247 pinctrl-names = "default", "sleep"; 248 pinctrl-0 = <&pinctrl_fec1>; 249 pinctrl-1 = <&pinctrl_fec1_sleep>; 250 fsl,magic-packet; 251 phy-handle = <ðphy0>; 252 phy-mode = "rgmii-id"; 253 254 mdio { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 258 ethphy0: ethernet-phy@7 { 259 compatible = "ethernet-phy-ieee802.3-c22"; 260 reg = <7>; 261 interrupt-parent = <&lsio_gpio1>; 262 interrupts = <29 IRQ_TYPE_LEVEL_LOW>; 263 micrel,led-mode = <0>; 264 reset-assert-us = <2>; 265 reset-deassert-us = <2>; 266 reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; 267 reset-names = "phy"; 268 }; 269 }; 270}; 271 272/* Apalis CAN1 */ 273&flexcan1 { 274 pinctrl-names = "default"; 275 pinctrl-0 = <&pinctrl_flexcan1>; 276}; 277 278/* Apalis CAN2 */ 279&flexcan2 { 280 pinctrl-names = "default"; 281 pinctrl-0 = <&pinctrl_flexcan2>; 282}; 283 284/* Apalis CAN3 (optional) */ 285&flexcan3 { 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_flexcan3>; 288}; 289 290/* TODO: Apalis HDMI1 */ 291 292/* On-module I2C */ 293&i2c1 { 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_lpi2c1>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 clock-frequency = <100000>; 299 status = "okay"; 300 301 /* TODO: Audio Codec */ 302 303 /* USB3503A */ 304 usb-hub@8 { 305 compatible = "smsc,usb3503a"; 306 reg = <0x08>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_usb3503a>; 309 connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>; 310 initial-mode = <1>; 311 intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>; 312 refclk-frequency = <25000000>; 313 reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>; 314 }; 315}; 316 317/* Apalis I2C1 */ 318&i2c2 { 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pinctrl_lpi2c2>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 clock-frequency = <100000>; 324 325 atmel_mxt_ts: touch@4a { 326 compatible = "atmel,maxtouch"; 327 reg = <0x4a>; 328 interrupt-parent = <&lsio_gpio4>; 329 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>; 332 reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_LOW>; /* Apalis GPIO6 */ 333 status = "disabled"; 334 }; 335 336 /* M41T0M6 real time clock on carrier board */ 337 rtc_i2c: rtc@68 { 338 compatible = "st,m41t0"; 339 reg = <0x68>; 340 status = "disabled"; 341 }; 342}; 343 344/* Apalis I2C3 (CAM) */ 345&i2c3 { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&pinctrl_lpi2c3>; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 clock-frequency = <100000>; 351}; 352 353&jpegdec { 354 status = "okay"; 355}; 356 357&jpegenc { 358 status = "okay"; 359}; 360 361/* TODO: Apalis LVDS1 */ 362 363/* Apalis SPI1 */ 364&lpspi0 { 365 pinctrl-names = "default"; 366 pinctrl-0 = <&pinctrl_lpspi0>; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>; 370}; 371 372/* Apalis SPI2 */ 373&lpspi2 { 374 pinctrl-names = "default"; 375 pinctrl-0 = <&pinctrl_lpspi2>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>; 379}; 380 381/* Apalis UART3 */ 382&lpuart0 { 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_lpuart0>; 385}; 386 387/* Apalis UART1 */ 388&lpuart1 { 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_lpuart1>; 391}; 392 393/* Apalis UART4 */ 394&lpuart2 { 395 pinctrl-names = "default"; 396 pinctrl-0 = <&pinctrl_lpuart2>; 397}; 398 399/* Apalis UART2 */ 400&lpuart3 { 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_lpuart3>; 403}; 404 405&lsio_gpio0 { 406 gpio-line-names = "MXM3_279", 407 "MXM3_277", 408 "MXM3_135", 409 "MXM3_203", 410 "MXM3_201", 411 "MXM3_275", 412 "MXM3_110", 413 "MXM3_120", 414 "MXM3_1/GPIO1", 415 "MXM3_3/GPIO2", 416 "MXM3_124", 417 "MXM3_122", 418 "MXM3_5/GPIO3", 419 "MXM3_7/GPIO4", 420 "", 421 "", 422 "MXM3_4", 423 "MXM3_211", 424 "MXM3_209", 425 "MXM3_2", 426 "MXM3_136", 427 "MXM3_134", 428 "MXM3_6", 429 "MXM3_8", 430 "MXM3_112", 431 "MXM3_118", 432 "MXM3_114", 433 "MXM3_116"; 434}; 435 436&lsio_gpio1 { 437 gpio-line-names = "", 438 "", 439 "", 440 "", 441 "MXM3_286", 442 "", 443 "MXM3_87", 444 "MXM3_99", 445 "MXM3_138", 446 "MXM3_140", 447 "MXM3_239", 448 "", 449 "MXM3_281", 450 "MXM3_283", 451 "MXM3_126", 452 "MXM3_132", 453 "", 454 "", 455 "", 456 "", 457 "MXM3_173", 458 "MXM3_175", 459 "MXM3_123"; 460 461 hdmi-ctrl-hog { 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_hdmi_ctrl>; 464 gpio-hog; 465 gpios = <30 GPIO_ACTIVE_HIGH>; 466 line-name = "CONNECTOR_IS_HDMI"; 467 /* Set signals depending on HDP device type, 0 DP, 1 HDMI */ 468 output-high; 469 }; 470}; 471 472&lsio_gpio2 { 473 gpio-line-names = "", 474 "", 475 "", 476 "", 477 "", 478 "", 479 "", 480 "MXM3_198", 481 "MXM3_35", 482 "MXM3_164", 483 "", 484 "", 485 "", 486 "", 487 "MXM3_217", 488 "MXM3_215", 489 "", 490 "", 491 "MXM3_193", 492 "MXM3_194", 493 "MXM3_37", 494 "", 495 "MXM3_271", 496 "MXM3_273", 497 "MXM3_195", 498 "MXM3_197", 499 "MXM3_177", 500 "MXM3_179", 501 "MXM3_181", 502 "MXM3_183", 503 "MXM3_185", 504 "MXM3_187"; 505 506 pcie-wifi-hog { 507 pinctrl-names = "default"; 508 pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; 509 gpio-hog; 510 gpios = <11 GPIO_ACTIVE_HIGH>; 511 line-name = "PCIE_WIFI_CLK"; 512 output-high; 513 }; 514}; 515 516&lsio_gpio3 { 517 gpio-line-names = "MXM3_191", 518 "", 519 "MXM3_221", 520 "MXM3_225", 521 "MXM3_223", 522 "MXM3_227", 523 "MXM3_200", 524 "MXM3_235", 525 "MXM3_231", 526 "MXM3_229", 527 "MXM3_233", 528 "MXM3_204", 529 "MXM3_196", 530 "", 531 "MXM3_202", 532 "", 533 "", 534 "", 535 "MXM3_305", 536 "MXM3_307", 537 "MXM3_309", 538 "MXM3_311", 539 "MXM3_315", 540 "MXM3_317", 541 "MXM3_319", 542 "MXM3_321", 543 "MXM3_15/GPIO7", 544 "MXM3_63", 545 "MXM3_17/GPIO8", 546 "MXM3_12", 547 "MXM3_14", 548 "MXM3_16"; 549}; 550 551&lsio_gpio4 { 552 gpio-line-names = "MXM3_18", 553 "MXM3_11/GPIO5", 554 "MXM3_13/GPIO6", 555 "MXM3_274", 556 "MXM3_84", 557 "MXM3_262", 558 "MXM3_96", 559 "", 560 "", 561 "", 562 "", 563 "", 564 "MXM3_190", 565 "", 566 "", 567 "", 568 "MXM3_269", 569 "MXM3_251", 570 "MXM3_253", 571 "MXM3_295", 572 "MXM3_299", 573 "MXM3_301", 574 "MXM3_297", 575 "MXM3_293", 576 "MXM3_291", 577 "MXM3_289", 578 "MXM3_287"; 579 580 /* Enable pcie root / sata ref clock unconditionally */ 581 pcie-sata-hog { 582 pinctrl-names = "default"; 583 pinctrl-0 = <&pinctrl_pcie_sata_refclk>; 584 gpio-hog; 585 gpios = <11 GPIO_ACTIVE_HIGH>; 586 line-name = "PCIE_SATA_CLK"; 587 output-high; 588 }; 589}; 590 591&lsio_gpio5 { 592 gpio-line-names = "", 593 "", 594 "", 595 "", 596 "", 597 "", 598 "", 599 "", 600 "", 601 "", 602 "", 603 "", 604 "", 605 "", 606 "MXM3_150", 607 "MXM3_160", 608 "MXM3_162", 609 "MXM3_144", 610 "MXM3_146", 611 "MXM3_148", 612 "MXM3_152", 613 "MXM3_156", 614 "MXM3_158", 615 "MXM3_159", 616 "MXM3_184", 617 "MXM3_180", 618 "MXM3_186", 619 "MXM3_188", 620 "MXM3_176", 621 "MXM3_178"; 622}; 623 624&lsio_gpio6 { 625 gpio-line-names = "", 626 "", 627 "", 628 "", 629 "", 630 "", 631 "", 632 "", 633 "", 634 "", 635 "MXM3_261", 636 "MXM3_263", 637 "MXM3_259", 638 "MXM3_257", 639 "MXM3_255", 640 "MXM3_128", 641 "MXM3_130", 642 "MXM3_265", 643 "MXM3_249", 644 "MXM3_247", 645 "MXM3_245", 646 "MXM3_243"; 647}; 648 649/* Apalis PWM3, MXM3 pin 6 */ 650&lsio_pwm0 { 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pinctrl_pwm0>; 653 #pwm-cells = <3>; 654}; 655 656/* Apalis PWM4, MXM3 pin 8 */ 657&lsio_pwm1 { 658 pinctrl-names = "default"; 659 pinctrl-0 = <&pinctrl_pwm1>; 660 #pwm-cells = <3>; 661}; 662 663/* Apalis PWM1, MXM3 pin 2 */ 664&lsio_pwm2 { 665 pinctrl-names = "default"; 666 pinctrl-0 = <&pinctrl_pwm2>; 667 #pwm-cells = <3>; 668}; 669 670/* Apalis PWM2, MXM3 pin 4 */ 671&lsio_pwm3 { 672 pinctrl-names = "default"; 673 pinctrl-0 = <&pinctrl_pwm3>; 674 #pwm-cells = <3>; 675}; 676 677/* Messaging Units */ 678&mu_m0 { 679 status = "okay"; 680}; 681 682&mu1_m0 { 683 status = "okay"; 684}; 685 686&mu2_m0 { 687 status = "okay"; 688}; 689 690/* TODO: Apalis PCIE1 */ 691 692/* TODO: On-module Wi-Fi */ 693 694/* TODO: Apalis BKL1_PWM */ 695 696/* TODO: Apalis DAP1 */ 697 698/* TODO: Analogue Audio */ 699 700/* TODO: Apalis SATA1 */ 701 702/* TODO: Apalis SPDIF1 */ 703 704/* TODO: Thermal Zones */ 705 706/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ 707 708/* TODO: Apalis USBH4 */ 709 710/* Apalis USBO1 */ 711&usbphy1 { 712 phy-3p0-supply = <®_usb_phy>; 713 status = "okay"; 714}; 715 716&usbotg1 { 717 pinctrl-names = "default"; 718 pinctrl-0 = <&pinctrl_usbotg1>; 719 adp-disable; 720 hnp-disable; 721 over-current-active-low; 722 power-active-high; 723 srp-disable; 724}; 725 726/* On-module eMMC */ 727&usdhc1 { 728 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 729 pinctrl-0 = <&pinctrl_usdhc1>; 730 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 731 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 732 bus-width = <8>; 733 non-removable; 734 status = "okay"; 735}; 736 737/* Apalis MMC1 */ 738&usdhc2 { 739 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 740 pinctrl-0 = <&pinctrl_usdhc2_4bit>, 741 <&pinctrl_usdhc2_8bit>, 742 <&pinctrl_mmc1_cd>; 743 pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, 744 <&pinctrl_usdhc2_8bit_100mhz>, 745 <&pinctrl_mmc1_cd>; 746 pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, 747 <&pinctrl_usdhc2_8bit_200mhz>, 748 <&pinctrl_mmc1_cd>; 749 pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, 750 <&pinctrl_usdhc2_8bit_sleep>, 751 <&pinctrl_mmc1_cd_sleep>; 752 bus-width = <8>; 753 cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ 754 no-1-8-v; 755}; 756 757/* Apalis SD1 */ 758&usdhc3 { 759 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 760 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; 761 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>; 762 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>; 763 bus-width = <4>; 764 cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */ 765 no-1-8-v; 766}; 767 768/* Video Processing Unit */ 769&vpu { 770 compatible = "nxp,imx8qm-vpu"; 771 status = "okay"; 772}; 773 774&vpu_core0 { 775 reg = <0x2d080000 0x10000>; 776 memory-region = <&decoder_boot>, <&decoder_rpc>; 777 status = "okay"; 778}; 779 780&vpu_core1 { 781 reg = <0x2d090000 0x10000>; 782 memory-region = <&encoder1_boot>, <&encoder1_rpc>; 783 status = "okay"; 784}; 785 786&vpu_core2 { 787 reg = <0x2d0a0000 0x10000>; 788 memory-region = <&encoder2_boot>, <&encoder2_rpc>; 789 status = "okay"; 790}; 791 792&iomuxc { 793 pinctrl-names = "default"; 794 pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, 795 <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, 796 <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>, 797 <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>, 798 <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, 799 <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, 800 <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>, 801 <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>, 802 <&pinctrl_usdhc1_gpios>; 803 804 /* Apalis AN1_ADC */ 805 pinctrl_adc0: adc0grp { 806 fsl,pins = /* Apalis AN1_ADC0 */ 807 <IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060>, 808 /* Apalis AN1_ADC1 */ 809 <IMX8QM_ADC_IN1_DMA_ADC0_IN1 0xc0000060>, 810 /* Apalis AN1_ADC2 */ 811 <IMX8QM_ADC_IN2_DMA_ADC0_IN2 0xc0000060>, 812 /* Apalis AN1_TSWIP_ADC3 */ 813 <IMX8QM_ADC_IN3_DMA_ADC0_IN3 0xc0000060>; 814 }; 815 816 /* Apalis AN1_TS */ 817 pinctrl_adc1: adc1grp { 818 fsl,pins = /* Apalis AN1_TSPX */ 819 <IMX8QM_ADC_IN4_DMA_ADC1_IN0 0xc0000060>, 820 /* Apalis AN1_TSMX */ 821 <IMX8QM_ADC_IN5_DMA_ADC1_IN1 0xc0000060>, 822 /* Apalis AN1_TSPY */ 823 <IMX8QM_ADC_IN6_DMA_ADC1_IN2 0xc0000060>, 824 /* Apalis AN1_TSMY */ 825 <IMX8QM_ADC_IN7_DMA_ADC1_IN3 0xc0000060>; 826 }; 827 828 /* Apalis CAM1 */ 829 pinctrl_cam1_gpios: cam1gpiosgrp { 830 fsl,pins = /* Apalis CAM1_D7 */ 831 <IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021>, 832 /* Apalis CAM1_D6 */ 833 <IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021>, 834 /* Apalis CAM1_D5 */ 835 <IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021>, 836 /* Apalis CAM1_D4 */ 837 <IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021>, 838 /* Apalis CAM1_D3 */ 839 <IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021>, 840 /* Apalis CAM1_D2 */ 841 <IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021>, 842 /* Apalis CAM1_D1 */ 843 <IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021>, 844 /* Apalis CAM1_D0 */ 845 <IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021>, 846 /* Apalis CAM1_PCLK */ 847 <IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021>, 848 /* Apalis CAM1_MCLK */ 849 <IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021>, 850 /* Apalis CAM1_VSYNC */ 851 <IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021>, 852 /* Apalis CAM1_HSYNC */ 853 <IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021>; 854 }; 855 856 /* Apalis DAP1 */ 857 pinctrl_dap1_gpios: dap1gpiosgrp { 858 fsl,pins = /* Apalis DAP1_MCLK */ 859 <IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021>, 860 /* Apalis DAP1_D_OUT */ 861 <IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021>, 862 /* Apalis DAP1_RESET */ 863 <IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021>, 864 /* Apalis DAP1_BIT_CLK */ 865 <IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021>, 866 /* Apalis DAP1_D_IN */ 867 <IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021>, 868 /* Apalis DAP1_SYNC */ 869 <IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021>, 870 /* On-module Wi-Fi_I2S_EN# */ 871 <IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021>; 872 }; 873 874 /* Apalis LCD1_G1+2 */ 875 pinctrl_esai0_gpios: esai0gpiosgrp { 876 fsl,pins = /* Apalis LCD1_G1 */ 877 <IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021>, 878 /* Apalis LCD1_G2 */ 879 <IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021>; 880 }; 881 882 /* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */ 883 pinctrl_fec1: fec1grp { 884 fsl,pins = /* Use pads in 3.3V mode */ 885 <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>, 886 <IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020>, 887 <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>, 888 <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020>, 889 <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020>, 890 <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020>, 891 <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020>, 892 <IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020>, 893 <IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020>, 894 <IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020>, 895 <IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020>, 896 <IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020>, 897 <IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020>, 898 <IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020>, 899 <IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020>, 900 <IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020>, 901 /* On-module ETH_RESET# */ 902 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>, 903 /* On-module ETH_INT# */ 904 <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000060>; 905 }; 906 907 pinctrl_fec1_sleep: fec1-sleepgrp { 908 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>, 909 <IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040>, 910 <IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040>, 911 <IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040>, 912 <IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040>, 913 <IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040>, 914 <IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040>, 915 <IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040>, 916 <IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040>, 917 <IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040>, 918 <IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040>, 919 <IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040>, 920 <IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040>, 921 <IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040>, 922 <IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040>, 923 <IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040>, 924 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>, 925 <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000040>; 926 }; 927 928 /* Apalis LCD1_ */ 929 pinctrl_fec2_gpios: fec2gpiosgrp { 930 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0>, 931 /* Apalis LCD1_R1 */ 932 <IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021>, 933 /* Apalis LCD1_R0 */ 934 <IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021>, 935 /* Apalis LCD1_G0 */ 936 <IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021>, 937 /* Apalis LCD1_R7 */ 938 <IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021>, 939 /* Apalis LCD1_DE */ 940 <IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021>, 941 /* Apalis LCD1_HSYNC */ 942 <IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021>, 943 /* Apalis LCD1_VSYNC */ 944 <IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021>, 945 /* Apalis LCD1_PCLK */ 946 <IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021>, 947 /* Apalis LCD1_R6 */ 948 <IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021>, 949 /* Apalis LCD1_R5 */ 950 <IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021>, 951 /* Apalis LCD1_R4 */ 952 <IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021>, 953 /* Apalis LCD1_R3 */ 954 <IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021>, 955 /* Apalis LCD1_R2 */ 956 <IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021>; 957 }; 958 959 /* Apalis CAN1 */ 960 pinctrl_flexcan1: flexcan0grp { 961 fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021>, 962 <IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021>; 963 }; 964 965 /* Apalis CAN2 */ 966 pinctrl_flexcan2: flexcan1grp { 967 fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021>, 968 <IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021>; 969 }; 970 971 /* Apalis CAN3 (optional) */ 972 pinctrl_flexcan3: flexcan2grp { 973 fsl,pins = <IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x00000021>, 974 <IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x00000021>; 975 }; 976 977 /* Apalis GPIO1 */ 978 pinctrl_gpio1: gpio1grp { 979 fsl,pins = <IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021>; 980 }; 981 982 /* Apalis GPIO2 */ 983 pinctrl_gpio2: gpio2grp { 984 fsl,pins = <IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021>; 985 }; 986 987 /* Apalis GPIO3 */ 988 pinctrl_gpio3: gpio3grp { 989 fsl,pins = <IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021>; 990 }; 991 992 /* Apalis GPIO4 */ 993 pinctrl_gpio4: gpio4grp { 994 fsl,pins = <IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021>; 995 }; 996 997 /* Apalis GPIO5 */ 998 pinctrl_gpio5: gpio5grp { 999 fsl,pins = <IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021>; 1000 }; 1001 1002 /* Apalis GPIO6 */ 1003 pinctrl_gpio6: gpio6grp { 1004 fsl,pins = <IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x00000021>; 1005 }; 1006 1007 /* Apalis GPIO7 */ 1008 pinctrl_gpio7: gpio7grp { 1009 fsl,pins = <IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 0x00000021>; 1010 }; 1011 1012 /* Apalis GPIO8 */ 1013 pinctrl_gpio8: gpio8grp { 1014 fsl,pins = <IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 0x00000021>; 1015 }; 1016 1017 /* Apalis BKL1_ON */ 1018 pinctrl_gpio_bkl_on: gpiobklongrp { 1019 fsl,pins = <IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021>; 1020 }; 1021 1022 /* Apalis WAKE1_MICO */ 1023 pinctrl_gpio_keys: gpiokeysgrp { 1024 fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 0x06700021>; 1025 }; 1026 1027 /* Apalis USBH_OC# */ 1028 pinctrl_gpio_usbh_oc_n: gpiousbhocngrp { 1029 fsl,pins = <IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x04000021>; 1030 }; 1031 1032 /* On-module HDMI_CTRL */ 1033 pinctrl_hdmi_ctrl: hdmictrlgrp { 1034 fsl,pins = <IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000061>; 1035 }; 1036 1037 /* On-module I2C */ 1038 pinctrl_lpi2c1: lpi2c1grp { 1039 fsl,pins = <IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x04000020>, 1040 <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020>; 1041 }; 1042 1043 /* Apalis I2C1 */ 1044 pinctrl_lpi2c2: lpi2c2grp { 1045 fsl,pins = <IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0x04000020>, 1046 <IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020>; 1047 }; 1048 1049 /* Apalis I2C3 (CAM) */ 1050 pinctrl_lpi2c3: lpi2c3grp { 1051 fsl,pins = <IMX8QM_SIM0_PD_DMA_I2C3_SCL 0x04000020>, 1052 <IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020>; 1053 }; 1054 1055 /* Apalis SPI1 */ 1056 pinctrl_lpspi0: lpspi0grp { 1057 fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x0600004c>, 1058 <IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x0600004c>, 1059 <IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x0600004c>, 1060 <IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x0600004c>; 1061 }; 1062 1063 /* Apalis SPI2 */ 1064 pinctrl_lpspi2: lpspi2grp { 1065 fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c>, 1066 <IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c>, 1067 <IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c>, 1068 <IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x0600004c>; 1069 }; 1070 1071 /* Apalis UART3 */ 1072 pinctrl_lpuart0: lpuart0grp { 1073 fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020>, 1074 <IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020>; 1075 }; 1076 1077 /* Apalis UART1 */ 1078 pinctrl_lpuart1: lpuart1grp { 1079 fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020>, 1080 <IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020>, 1081 <IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020>, 1082 <IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020>; 1083 }; 1084 1085 /* Apalis UART1 */ 1086 pinctrl_lpuart1ctrl: lpuart1ctrlgrp { 1087 fsl,pins = /* Apalis UART1_DTR */ 1088 <IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021>, 1089 /* Apalis UART1_DSR */ 1090 <IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021>, 1091 /* Apalis UART1_DCD */ 1092 <IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021>, 1093 /* Apalis UART1_RI */ 1094 <IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021>; 1095 }; 1096 1097 /* Apalis UART4 */ 1098 pinctrl_lpuart2: lpuart2grp { 1099 fsl,pins = <IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020>, 1100 <IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020>; 1101 }; 1102 1103 /* Apalis UART2 */ 1104 pinctrl_lpuart3: lpuart3grp { 1105 fsl,pins = <IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020>, 1106 <IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020>, 1107 <IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020>, 1108 <IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020>; 1109 }; 1110 1111 /* Apalis TS_2 */ 1112 pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp { 1113 fsl,pins = <IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021>; 1114 }; 1115 1116 /* Apalis LCD1_G6+7 */ 1117 pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp { 1118 fsl,pins = /* Apalis LCD1_G6 */ 1119 <IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021>, 1120 /* Apalis LCD1_G7 */ 1121 <IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021>; 1122 }; 1123 1124 /* Apalis TS_3 */ 1125 pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp { 1126 fsl,pins = <IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021>; 1127 }; 1128 1129 /* Apalis TS_4 */ 1130 pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp { 1131 fsl,pins = <IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021>; 1132 }; 1133 1134 /* Apalis TS_1 */ 1135 pinctrl_mlb_gpios: mlbgpiosgrp { 1136 fsl,pins = <IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 0x00000021>; 1137 }; 1138 1139 /* Apalis MMC1_CD# */ 1140 pinctrl_mmc1_cd: mmc1cdgrp { 1141 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021>; 1142 }; 1143 1144 pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp { 1145 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x04000021>; 1146 }; 1147 1148 /* On-module PCIe_Wi-Fi */ 1149 pinctrl_pcieb: pciebgrp { 1150 fsl,pins = <IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021>, 1151 <IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021>, 1152 <IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021>; 1153 }; 1154 1155 /* On-module PCIe_CLK_EN1 */ 1156 pinctrl_pcie_sata_refclk: pciesatarefclkgrp { 1157 fsl,pins = <IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021>; 1158 }; 1159 1160 /* On-module PCIe_CLK_EN2 */ 1161 pinctrl_pcie_wifi_refclk: pciewifirefclkgrp { 1162 fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 0x00000021>; 1163 }; 1164 1165 /* Apalis PWM3 */ 1166 pinctrl_pwm0: pwm0grp { 1167 fsl,pins = <IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT 0x00000020>; 1168 }; 1169 1170 /* Apalis PWM4 */ 1171 pinctrl_pwm1: pwm1grp { 1172 fsl,pins = <IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT 0x00000020>; 1173 }; 1174 1175 /* Apalis PWM1 */ 1176 pinctrl_pwm2: pwm2grp { 1177 fsl,pins = <IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT 0x00000020>; 1178 }; 1179 1180 /* Apalis PWM2 */ 1181 pinctrl_pwm3: pwm3grp { 1182 fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT 0x00000020>; 1183 }; 1184 1185 /* Apalis BKL1_PWM */ 1186 pinctrl_pwm_bkl: pwmbklgrp { 1187 fsl,pins = <IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020>; 1188 }; 1189 1190 /* Apalis LCD1_ */ 1191 pinctrl_qspi1a_gpios: qspi1agpiosgrp { 1192 fsl,pins = /* Apalis LCD1_B0 */ 1193 <IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021>, 1194 /* Apalis LCD1_B1 */ 1195 <IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021>, 1196 /* Apalis LCD1_B2 */ 1197 <IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021>, 1198 /* Apalis LCD1_B3 */ 1199 <IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021>, 1200 /* Apalis LCD1_B5 */ 1201 <IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021>, 1202 /* Apalis LCD1_B7 */ 1203 <IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021>, 1204 /* Apalis LCD1_B4 */ 1205 <IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021>, 1206 /* Apalis LCD1_B6 */ 1207 <IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021>; 1208 }; 1209 1210 /* On-module RESET_MOCI#_DRV */ 1211 pinctrl_reset_moci: resetmocigrp { 1212 fsl,pins = <IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021>; 1213 }; 1214 1215 /* On-module I2S SGTL5000 for Apalis Analogue Audio */ 1216 pinctrl_sai1: sai1grp { 1217 fsl,pins = <IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0xc600006c>, 1218 <IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0xc600004c>, 1219 <IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0xc600004c>, 1220 <IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0xc600004c>; 1221 }; 1222 1223 /* Apalis SATA1_ACT# */ 1224 pinctrl_sata1_act: sata1actgrp { 1225 fsl,pins = <IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021>; 1226 }; 1227 1228 /* Apalis SD1_CD# */ 1229 pinctrl_sd1_cd: sd1cdgrp { 1230 fsl,pins = <IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021>; 1231 }; 1232 1233 /* On-module I2S SGTL5000 SYS_MCLK */ 1234 pinctrl_sgtl5000: sgtl5000grp { 1235 fsl,pins = <IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c>; 1236 }; 1237 1238 /* Apalis LCD1_ */ 1239 pinctrl_sim0_gpios: sim0gpiosgrp { 1240 fsl,pins = /* Apalis LCD1_G5 */ 1241 <IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021>, 1242 /* Apalis LCD1_G3 */ 1243 <IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021>, 1244 /* Apalis TS_5 */ 1245 <IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 0x00000021>, 1246 /* Apalis LCD1_G4 */ 1247 <IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 0x00000021>; 1248 }; 1249 1250 /* Apalis SPDIF */ 1251 pinctrl_spdif0: spdif0grp { 1252 fsl,pins = <IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040>, 1253 <IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040>; 1254 }; 1255 1256 pinctrl_touchctrl_gpios: touchctrlgpiosgrp { 1257 fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000021>, 1258 <IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041>, 1259 <IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021>, 1260 <IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 0x00000041>; 1261 }; 1262 1263 pinctrl_touchctrl_idle: touchctrlidlegrp { 1264 fsl,pins = <IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 0x00000021>, 1265 <IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 0x00000021>, 1266 <IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021>, 1267 <IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 0x00000021>; 1268 }; 1269 1270 /* On-module USB HSIC HUB (active) */ 1271 pinctrl_usb_hsic_active: usbh1activegrp { 1272 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0x000000cf>, 1273 <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0x000000ff>; 1274 }; 1275 1276 /* On-module USB HSIC HUB (idle) */ 1277 pinctrl_usb_hsic_idle: usbh1idlegrp { 1278 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0x000000cf>, 1279 <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0x000000cf>; 1280 }; 1281 1282 /* On-module USB HSIC HUB */ 1283 pinctrl_usb3503a: usb3503agrp { 1284 fsl,pins = /* On-module HSIC_HUB_CONNECT */ 1285 <IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x00000041>, 1286 /* On-module HSIC_INT_N */ 1287 <IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021>, 1288 /* On-module HSIC_RESET_N */ 1289 <IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000041>; 1290 }; 1291 1292 /* Apalis USBH_EN */ 1293 pinctrl_usbh_en: usbhengrp { 1294 fsl,pins = <IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021>; 1295 }; 1296 1297 /* Apalis USBO1 */ 1298 pinctrl_usbotg1: usbotg1grp { 1299 fsl,pins = /* Apalis USBO1_EN */ 1300 <IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>, 1301 /* Apalis USBO1_OC# */ 1302 <IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC 0x04000021>; 1303 }; 1304 1305 /* On-module eMMC */ 1306 pinctrl_usdhc1: usdhc1grp { 1307 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>, 1308 <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>, 1309 <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>, 1310 <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>, 1311 <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>, 1312 <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>, 1313 <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>, 1314 <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>, 1315 <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>, 1316 <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>, 1317 <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041>, 1318 <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>; 1319 }; 1320 1321 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1322 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>, 1323 <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>, 1324 <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>, 1325 <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>, 1326 <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>, 1327 <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>, 1328 <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>, 1329 <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>, 1330 <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>, 1331 <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>, 1332 <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040>, 1333 <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020>; 1334 }; 1335 1336 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1337 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>, 1338 <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>, 1339 <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>, 1340 <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>, 1341 <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>, 1342 <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>, 1343 <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>, 1344 <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>, 1345 <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>, 1346 <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>, 1347 <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040>, 1348 <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020>; 1349 }; 1350 1351 /* Apalis TS_6 */ 1352 pinctrl_usdhc1_gpios: usdhc1gpiosgrp { 1353 fsl,pins = <IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021>; 1354 }; 1355 1356 /* Apalis MMC1 */ 1357 pinctrl_usdhc2_4bit: usdhc2grp4bitgrp { 1358 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, 1359 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>, 1360 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>, 1361 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>, 1362 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>, 1363 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>, 1364 /* On-module PMIC use */ 1365 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 1366 }; 1367 1368 pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp { 1369 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, 1370 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, 1371 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, 1372 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, 1373 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, 1374 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, 1375 /* On-module PMIC use */ 1376 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 1377 }; 1378 1379 pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp { 1380 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, 1381 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, 1382 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, 1383 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, 1384 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, 1385 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, 1386 /* On-module PMIC use */ 1387 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 1388 }; 1389 1390 pinctrl_usdhc2_8bit: usdhc2grp8bitgrp { 1391 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021>, 1392 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021>, 1393 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021>, 1394 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021>; 1395 }; 1396 1397 pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp { 1398 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020>, 1399 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020>, 1400 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020>, 1401 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020>; 1402 }; 1403 1404 pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp { 1405 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020>, 1406 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020>, 1407 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020>, 1408 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020>; 1409 }; 1410 1411 pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp { 1412 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x04000061>, 1413 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x04000061>, 1414 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x04000061>, 1415 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x04000061>, 1416 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x04000061>, 1417 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x04000061>, 1418 /* On-module PMIC use */ 1419 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; 1420 }; 1421 1422 pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp { 1423 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x04000061>, 1424 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x04000061>, 1425 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x04000061>, 1426 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x04000061>; 1427 }; 1428 1429 /* Apalis SD1 */ 1430 pinctrl_usdhc3: usdhc3grp { 1431 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>, 1432 <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>, 1433 <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>, 1434 <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>, 1435 <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>, 1436 <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>, 1437 /* On-module PMIC use */ 1438 <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>; 1439 }; 1440 1441 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1442 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>, 1443 <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>, 1444 <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>, 1445 <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>, 1446 <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>, 1447 <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>, 1448 /* On-module PMIC use */ 1449 <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>; 1450 }; 1451 1452 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1453 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>, 1454 <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>, 1455 <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>, 1456 <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>, 1457 <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>, 1458 <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>, 1459 /* On-module PMIC use */ 1460 <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>; 1461 }; 1462 1463 /* On-module Wi-Fi */ 1464 pinctrl_wifi: wifigrp { 1465 fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */ 1466 <IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x06000021>, 1467 /* On-module Wi-Fi_PCIE_W_DISABLE */ 1468 <IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x06000021>; 1469 }; 1470 1471 pinctrl_wifi_pdn: wifipdngrp { 1472 fsl,pins = /* On-module Wi-Fi_POWER_DOWN */ 1473 <IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021>; 1474 }; 1475}; 1476