1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree file for LX2162AQDS 4// 5// Copyright 2020 NXP 6 7/dts-v1/; 8 9#include "fsl-lx2160a.dtsi" 10 11/ { 12 model = "NXP Layerscape LX2162AQDS"; 13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a"; 14 15 aliases { 16 crypto = &crypto; 17 mmc0 = &esdhc0; 18 mmc1 = &esdhc1; 19 serial0 = &uart0; 20 }; 21 22 chosen { 23 stdout-path = "serial0:115200n8"; 24 }; 25 26 sb_3v3: regulator-sb3v3 { 27 compatible = "regulator-fixed"; 28 regulator-name = "LTM4619-3.3VSB"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 }; 32 33 mdio-mux-1 { 34 compatible = "mdio-mux-multiplexer"; 35 mux-controls = <&mux 0>; 36 mdio-parent-bus = <&emdio1>; 37 #address-cells=<1>; 38 #size-cells = <0>; 39 40 mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */ 41 reg = <0x00>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 rgmii_phy1: ethernet-phy@1 { 46 compatible = "ethernet-phy-id001c.c916"; 47 reg = <0x1>; 48 eee-broken-1000t; 49 }; 50 }; 51 52 mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */ 53 reg = <0x8>; 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 rgmii_phy2: ethernet-phy@2 { 58 compatible = "ethernet-phy-id001c.c916"; 59 reg = <0x2>; 60 eee-broken-1000t; 61 }; 62 }; 63 64 mdio@18 { /* Slot #1 */ 65 reg = <0x18>; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 }; 69 70 mdio@19 { /* Slot #2 */ 71 reg = <0x19>; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 }; 75 76 mdio@1a { /* Slot #3 */ 77 reg = <0x1a>; 78 #address-cells = <1>; 79 #size-cells = <0>; 80 }; 81 82 mdio@1b { /* Slot #4 */ 83 reg = <0x1b>; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 }; 87 88 mdio@1c { /* Slot #5 */ 89 reg = <0x1c>; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 }; 93 94 mdio@1d { /* Slot #6 */ 95 reg = <0x1d>; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 }; 99 100 mdio@1e { /* Slot #7 */ 101 reg = <0x1e>; 102 #address-cells = <1>; 103 #size-cells = <0>; 104 }; 105 106 mdio@1f { /* Slot #8 */ 107 reg = <0x1f>; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 }; 111 }; 112 113 mdio-mux-2 { 114 compatible = "mdio-mux-multiplexer"; 115 mux-controls = <&mux 1>; 116 mdio-parent-bus = <&emdio2>; 117 #address-cells=<1>; 118 #size-cells = <0>; 119 120 mdio@0 { /* Slot #1 (secondary EMI) */ 121 reg = <0x00>; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 }; 125 126 mdio@1 { /* Slot #2 (secondary EMI) */ 127 reg = <0x01>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 }; 131 132 mdio@2 { /* Slot #3 (secondary EMI) */ 133 reg = <0x02>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 138 mdio@3 { /* Slot #4 (secondary EMI) */ 139 reg = <0x03>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 }; 143 144 mdio@4 { /* Slot #5 (secondary EMI) */ 145 reg = <0x04>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 }; 149 150 mdio@5 { /* Slot #6 (secondary EMI) */ 151 reg = <0x05>; 152 #address-cells = <1>; 153 #size-cells = <0>; 154 }; 155 156 mdio@6 { /* Slot #7 (secondary EMI) */ 157 reg = <0x06>; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 }; 161 162 mdio@7 { /* Slot #8 (secondary EMI) */ 163 reg = <0x07>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 }; 167 }; 168}; 169 170&can0 { 171 status = "okay"; 172}; 173 174&can1 { 175 status = "okay"; 176}; 177 178&crypto { 179 status = "okay"; 180}; 181 182&dpmac17 { 183 phy-handle = <&rgmii_phy1>; 184 phy-connection-type = "rgmii-id"; 185}; 186 187&dpmac18 { 188 phy-handle = <&rgmii_phy2>; 189 phy-connection-type = "rgmii-id"; 190}; 191 192&dspi0 { 193 status = "okay"; 194 195 dflash0: flash@0 { 196 #address-cells = <1>; 197 #size-cells = <1>; 198 compatible = "jedec,spi-nor"; 199 reg = <0>; 200 spi-max-frequency = <1000000>; 201 }; 202}; 203 204&dspi1 { 205 status = "okay"; 206 207 dflash1: flash@0 { 208 #address-cells = <1>; 209 #size-cells = <1>; 210 compatible = "jedec,spi-nor"; 211 reg = <0>; 212 spi-max-frequency = <1000000>; 213 }; 214}; 215 216&dspi2 { 217 status = "okay"; 218 219 dflash2: flash@0 { 220 #address-cells = <1>; 221 #size-cells = <1>; 222 compatible = "jedec,spi-nor"; 223 reg = <0>; 224 spi-max-frequency = <1000000>; 225 }; 226}; 227 228&emdio1 { 229 status = "okay"; 230}; 231 232&emdio2 { 233 status = "okay"; 234}; 235 236&esdhc0 { 237 sd-uhs-sdr104; 238 sd-uhs-sdr50; 239 sd-uhs-sdr25; 240 sd-uhs-sdr12; 241 status = "okay"; 242}; 243 244&esdhc1 { 245 mmc-hs200-1_8v; 246 mmc-hs400-1_8v; 247 bus-width = <8>; 248 status = "okay"; 249}; 250 251&fspi { 252 status = "okay"; 253 254 mt35xu512aba0: flash@0 { 255 #address-cells = <1>; 256 #size-cells = <1>; 257 compatible = "jedec,spi-nor"; 258 m25p,fast-read; 259 spi-max-frequency = <50000000>; 260 reg = <0>; 261 spi-rx-bus-width = <8>; 262 spi-tx-bus-width = <8>; 263 }; 264}; 265 266&i2c0 { 267 status = "okay"; 268 269 fpga@66 { 270 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", 271 "simple-mfd"; 272 reg = <0x66>; 273 274 mux: mux-controller { 275 compatible = "reg-mux"; 276 #mux-control-cells = <1>; 277 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ 278 <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ 279 }; 280 }; 281 282 i2c-mux@77 { 283 compatible = "nxp,pca9547"; 284 reg = <0x77>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 288 i2c@2 { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 reg = <0x2>; 292 293 power-monitor@40 { 294 compatible = "ti,ina220"; 295 reg = <0x40>; 296 shunt-resistor = <500>; 297 }; 298 299 power-monitor@41 { 300 compatible = "ti,ina220"; 301 reg = <0x41>; 302 shunt-resistor = <1000>; 303 }; 304 }; 305 306 i2c@3 { 307 #address-cells = <1>; 308 #size-cells = <0>; 309 reg = <0x3>; 310 311 temperature-sensor@4c { 312 compatible = "nxp,sa56004"; 313 reg = <0x4c>; 314 vcc-supply = <&sb_3v3>; 315 }; 316 317 rtc@51 { 318 compatible = "nxp,pcf2129"; 319 reg = <0x51>; 320 /* IRQ_RTC_B -> IRQ11_B(CPLD) -> IRQ11(CPU), active low */ 321 interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>; 322 }; 323 }; 324 }; 325}; 326 327&optee { 328 status = "okay"; 329}; 330 331&sata0 { 332 status = "okay"; 333}; 334 335&sata1 { 336 status = "okay"; 337}; 338 339&sata2 { 340 status = "okay"; 341}; 342 343&sata3 { 344 status = "okay"; 345}; 346 347&uart0 { 348 status = "okay"; 349}; 350 351&uart1 { 352 status = "okay"; 353}; 354 355&usb0 { 356 status = "okay"; 357}; 358