xref: /linux/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts (revision 55d0969c451159cff86949b38c39171cab962069) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Device Tree file for LX2162A Clearfog
4//
5// Copyright 2023 Josua Mayer <josua@solid-run.com>
6
7/dts-v1/;
8
9#include "fsl-lx2160a.dtsi"
10#include "fsl-lx2162a-sr-som.dtsi"
11
12/ {
13	model = "SolidRun LX2162A Clearfog";
14	compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
15
16	aliases {
17		crypto = &crypto;
18		i2c0 = &i2c0;
19		i2c1 = &i2c2;
20		i2c2 = &i2c4;
21		i2c3 = &sfp_i2c0;
22		i2c4 = &sfp_i2c1;
23		i2c5 = &sfp_i2c2;
24		i2c6 = &sfp_i2c3;
25		i2c7 = &mpcie1_i2c;
26		i2c8 = &mpcie0_i2c;
27		i2c9 = &pcieclk_i2c;
28		i2c10 = &i2c5;
29		mmc0 = &esdhc0;
30		mmc1 = &esdhc1;
31		serial0 = &uart0;
32	};
33
34	chosen {
35		stdout-path = "serial0:115200n8";
36	};
37
38	leds {
39		compatible = "gpio-leds";
40
41		led_sfp_at: led-sfp-at {
42			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
43			default-state = "off";
44		};
45
46		led_sfp_ab: led-sfp-ab {
47			gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
48			default-state = "off";
49		};
50
51		led_sfp_bt: led-sfp-bt {
52			gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
53			default-state = "off";
54		};
55
56		led_sfp_bb: led-sfp-bb {
57			gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
58			default-state = "off";
59		};
60	};
61
62	sfp_at: sfp-at {
63		compatible = "sff,sfp";
64		i2c-bus = <&sfp_i2c0>;
65		mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
66		maximum-power-milliwatt = <2000>;
67	};
68
69	sfp_ab: sfp-ab {
70		compatible = "sff,sfp";
71		i2c-bus = <&sfp_i2c1>;
72		mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
73		maximum-power-milliwatt = <2000>;
74	};
75
76	sfp_bt: sfp-bt {
77		compatible = "sff,sfp";
78		i2c-bus = <&sfp_i2c2>;
79		mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
80		maximum-power-milliwatt = <2000>;
81	};
82
83	sfp_bb: sfp-bb {
84		compatible = "sff,sfp";
85		i2c-bus = <&sfp_i2c3>;
86		mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
87		maximum-power-milliwatt = <2000>;
88	};
89};
90
91&dpmac3 {
92	sfp = <&sfp_at>;
93	managed = "in-band-status";
94	phys = <&serdes_1 7>;
95};
96
97&dpmac4 {
98	sfp = <&sfp_ab>;
99	managed = "in-band-status";
100	phys = <&serdes_1 6>;
101};
102
103&dpmac5 {
104	sfp = <&sfp_bt>;
105	managed = "in-band-status";
106	phys = <&serdes_1 5>;
107};
108
109&dpmac6 {
110	sfp = <&sfp_bb>;
111	managed = "in-band-status";
112	phys = <&serdes_1 4>;
113};
114
115&dpmac11 {
116	phys = <&serdes_2 0>;
117	phy-handle = <&ethernet_phy3>;
118	phy-connection-type = "sgmii";
119	status = "okay";
120};
121
122&dpmac12 {
123	phys = <&serdes_2 1>;
124	phy-handle = <&ethernet_phy1>;
125	phy-connection-type = "sgmii";
126	status = "okay";
127};
128
129&dpmac13 {
130	phys = <&serdes_2 6>;
131	phy-handle = <&ethernet_phy6>;
132	phy-connection-type = "sgmii";
133	status = "okay";
134};
135
136&dpmac14 {
137	phys = <&serdes_2 7>;
138	phy-handle = <&ethernet_phy8>;
139	phy-connection-type = "sgmii";
140	status = "okay";
141};
142
143&dpmac15 {
144	phys = <&serdes_2 4>;
145	phy-handle = <&ethernet_phy4>;
146	phy-connection-type = "sgmii";
147	status = "okay";
148};
149
150&dpmac16 {
151	phys = <&serdes_2 5>;
152	phy-handle = <&ethernet_phy2>;
153	phy-connection-type = "sgmii";
154	status = "okay";
155};
156
157&dpmac17 {
158	/* override connection to on-SoM phy */
159	/delete-property/ phy-handle;
160	/delete-property/ phy-connection-type;
161
162	phys = <&serdes_2 2>;
163	phy-handle = <&ethernet_phy5>;
164	phy-connection-type = "sgmii";
165	status = "okay";
166};
167
168&dpmac18 {
169	phys = <&serdes_2 3>;
170	phy-handle = <&ethernet_phy7>;
171	phy-connection-type = "sgmii";
172	status = "okay";
173};
174
175&emdio1 {
176	ethernet_phy1: ethernet-phy@8 {
177		compatible = "ethernet-phy-ieee802.3-c45";
178		reg = <8>;
179		max-speed = <1000>;
180	};
181
182	ethernet_phy2: ethernet-phy@9 {
183		compatible = "ethernet-phy-ieee802.3-c45";
184		reg = <9>;
185		max-speed = <1000>;
186	};
187
188	ethernet_phy3: ethernet-phy@10 {
189		compatible = "ethernet-phy-ieee802.3-c45";
190		reg = <10>;
191		max-speed = <1000>;
192	};
193
194	ethernet_phy4: ethernet-phy@11 {
195		compatible = "ethernet-phy-ieee802.3-c45";
196		reg = <11>;
197		max-speed = <1000>;
198	};
199
200	ethernet_phy5: ethernet-phy@12 {
201		compatible = "ethernet-phy-ieee802.3-c45";
202		reg = <12>;
203		max-speed = <1000>;
204	};
205
206	ethernet_phy6: ethernet-phy@13 {
207		compatible = "ethernet-phy-ieee802.3-c45";
208		reg = <13>;
209		max-speed = <1000>;
210	};
211
212	ethernet_phy7: ethernet-phy@14 {
213		compatible = "ethernet-phy-ieee802.3-c45";
214		reg = <14>;
215		max-speed = <1000>;
216	};
217
218	ethernet_phy8: ethernet-phy@15 {
219		compatible = "ethernet-phy-ieee802.3-c45";
220		reg = <15>;
221		max-speed = <1000>;
222	};
223};
224
225&esdhc0 {
226	sd-uhs-sdr104;
227	sd-uhs-sdr50;
228	sd-uhs-sdr25;
229	sd-uhs-sdr12;
230	status = "okay";
231};
232
233&ethernet_phy0 {
234	/*
235	 * SoM has a phy at address 1 connected to SoC Ethernet Controller 1.
236	 * It competes for WRIOP MAC17, and no connector has been wired.
237	 */
238	status = "disabled";
239};
240
241&i2c2 {
242	status = "okay";
243
244	/* retimer@18 */
245
246	i2c-mux@70 {
247		compatible = "nxp,pca9546";
248		reg = <0x70>;
249		#address-cells = <1>;
250		#size-cells = <0>;
251		i2c-mux-idle-disconnect;
252
253		sfp_i2c0: i2c@0 {
254			#address-cells = <1>;
255			#size-cells = <0>;
256			reg = <0>;
257		};
258
259		sfp_i2c1: i2c@1 {
260			#address-cells = <1>;
261			#size-cells = <0>;
262			reg = <1>;
263		};
264
265		sfp_i2c2: i2c@2 {
266			#address-cells = <1>;
267			#size-cells = <0>;
268			reg = <2>;
269		};
270
271		sfp_i2c3: i2c@3 {
272			#address-cells = <1>;
273			#size-cells = <0>;
274			reg = <3>;
275		};
276	};
277
278	i2c-mux@71 {
279		compatible = "nxp,pca9546";
280		reg = <0x71>;
281		#address-cells = <1>;
282		#size-cells = <0>;
283		i2c-mux-idle-disconnect;
284
285		mpcie1_i2c: i2c@0 {
286			#address-cells = <1>;
287			#size-cells = <0>;
288			reg = <0>;
289		};
290
291		mpcie0_i2c: i2c@1 {
292			#address-cells = <1>;
293			#size-cells = <0>;
294			reg = <1>;
295		};
296
297		pcieclk_i2c: i2c@2 {
298			#address-cells = <1>;
299			#size-cells = <0>;
300			reg = <2>;
301
302			/* clock-controller@6b */
303		};
304	};
305};
306
307&pcie3 {
308	status = "disabled";
309};
310
311&pcie4 {
312	status = "disabled";
313};
314
315&pcs_mdio3 {
316	status = "okay";
317};
318
319&pcs_mdio4 {
320	status = "okay";
321};
322
323&pcs_mdio5 {
324	status = "okay";
325};
326
327&pcs_mdio6 {
328	status = "okay";
329};
330
331&pcs_mdio11 {
332	status = "okay";
333};
334
335&pcs_mdio12 {
336	status = "okay";
337};
338
339&pcs_mdio13 {
340	status = "okay";
341};
342
343&pcs_mdio14 {
344	status = "okay";
345};
346
347&pcs_mdio15 {
348	status = "okay";
349};
350
351&pcs_mdio16 {
352	status = "okay";
353};
354
355&pcs_mdio17 {
356	status = "okay";
357};
358
359&pcs_mdio18 {
360	status = "okay";
361};
362
363&serdes_1 {
364	status = "okay";
365};
366
367&serdes_2 {
368	status = "okay";
369};
370
371&uart0 {
372	status = "okay";
373};
374
375&usb0 {
376	status = "okay";
377};
378