1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/memreserve/ 0x80000000 0x00010000; 13 14/ { 15 compatible = "fsl,lx2160a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 rtc1 = &ftm_alarm0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 // 8 clusters having 2 Cortex-A72 cores each 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a72"; 32 enable-method = "psci"; 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 d-cache-size = <0x8000>; 36 d-cache-line-size = <64>; 37 d-cache-sets = <128>; 38 i-cache-size = <0xC000>; 39 i-cache-line-size = <64>; 40 i-cache-sets = <192>; 41 next-level-cache = <&cluster0_l2>; 42 cpu-idle-states = <&cpu_pw15>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a72"; 49 enable-method = "psci"; 50 reg = <0x1>; 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52 d-cache-size = <0x8000>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 i-cache-size = <0xC000>; 56 i-cache-line-size = <64>; 57 i-cache-sets = <192>; 58 next-level-cache = <&cluster0_l2>; 59 cpu-idle-states = <&cpu_pw15>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu100: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a72"; 66 enable-method = "psci"; 67 reg = <0x100>; 68 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 69 d-cache-size = <0x8000>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 i-cache-size = <0xC000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <192>; 75 next-level-cache = <&cluster1_l2>; 76 cpu-idle-states = <&cpu_pw15>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu101: cpu@101 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a72"; 83 enable-method = "psci"; 84 reg = <0x101>; 85 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 86 d-cache-size = <0x8000>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 i-cache-size = <0xC000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <192>; 92 next-level-cache = <&cluster1_l2>; 93 cpu-idle-states = <&cpu_pw15>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu200: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a72"; 100 enable-method = "psci"; 101 reg = <0x200>; 102 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 103 d-cache-size = <0x8000>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 i-cache-size = <0xC000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <192>; 109 next-level-cache = <&cluster2_l2>; 110 cpu-idle-states = <&cpu_pw15>; 111 #cooling-cells = <2>; 112 }; 113 114 cpu201: cpu@201 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a72"; 117 enable-method = "psci"; 118 reg = <0x201>; 119 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 120 d-cache-size = <0x8000>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <128>; 123 i-cache-size = <0xC000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <192>; 126 next-level-cache = <&cluster2_l2>; 127 cpu-idle-states = <&cpu_pw15>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu300: cpu@300 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a72"; 134 enable-method = "psci"; 135 reg = <0x300>; 136 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 137 d-cache-size = <0x8000>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <128>; 140 i-cache-size = <0xC000>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <192>; 143 next-level-cache = <&cluster3_l2>; 144 cpu-idle-states = <&cpu_pw15>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu301: cpu@301 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a72"; 151 enable-method = "psci"; 152 reg = <0x301>; 153 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 154 d-cache-size = <0x8000>; 155 d-cache-line-size = <64>; 156 d-cache-sets = <128>; 157 i-cache-size = <0xC000>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <192>; 160 next-level-cache = <&cluster3_l2>; 161 cpu-idle-states = <&cpu_pw15>; 162 #cooling-cells = <2>; 163 }; 164 165 cpu400: cpu@400 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a72"; 168 enable-method = "psci"; 169 reg = <0x400>; 170 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 i-cache-size = <0xC000>; 175 i-cache-line-size = <64>; 176 i-cache-sets = <192>; 177 next-level-cache = <&cluster4_l2>; 178 cpu-idle-states = <&cpu_pw15>; 179 #cooling-cells = <2>; 180 }; 181 182 cpu401: cpu@401 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a72"; 185 enable-method = "psci"; 186 reg = <0x401>; 187 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 188 d-cache-size = <0x8000>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <128>; 191 i-cache-size = <0xC000>; 192 i-cache-line-size = <64>; 193 i-cache-sets = <192>; 194 next-level-cache = <&cluster4_l2>; 195 cpu-idle-states = <&cpu_pw15>; 196 #cooling-cells = <2>; 197 }; 198 199 cpu500: cpu@500 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a72"; 202 enable-method = "psci"; 203 reg = <0x500>; 204 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 205 d-cache-size = <0x8000>; 206 d-cache-line-size = <64>; 207 d-cache-sets = <128>; 208 i-cache-size = <0xC000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <192>; 211 next-level-cache = <&cluster5_l2>; 212 cpu-idle-states = <&cpu_pw15>; 213 #cooling-cells = <2>; 214 }; 215 216 cpu501: cpu@501 { 217 device_type = "cpu"; 218 compatible = "arm,cortex-a72"; 219 enable-method = "psci"; 220 reg = <0x501>; 221 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 222 d-cache-size = <0x8000>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <128>; 225 i-cache-size = <0xC000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <192>; 228 next-level-cache = <&cluster5_l2>; 229 cpu-idle-states = <&cpu_pw15>; 230 #cooling-cells = <2>; 231 }; 232 233 cpu600: cpu@600 { 234 device_type = "cpu"; 235 compatible = "arm,cortex-a72"; 236 enable-method = "psci"; 237 reg = <0x600>; 238 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 239 d-cache-size = <0x8000>; 240 d-cache-line-size = <64>; 241 d-cache-sets = <128>; 242 i-cache-size = <0xC000>; 243 i-cache-line-size = <64>; 244 i-cache-sets = <192>; 245 next-level-cache = <&cluster6_l2>; 246 cpu-idle-states = <&cpu_pw15>; 247 #cooling-cells = <2>; 248 }; 249 250 cpu601: cpu@601 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 enable-method = "psci"; 254 reg = <0x601>; 255 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 256 d-cache-size = <0x8000>; 257 d-cache-line-size = <64>; 258 d-cache-sets = <128>; 259 i-cache-size = <0xC000>; 260 i-cache-line-size = <64>; 261 i-cache-sets = <192>; 262 next-level-cache = <&cluster6_l2>; 263 cpu-idle-states = <&cpu_pw15>; 264 #cooling-cells = <2>; 265 }; 266 267 cpu700: cpu@700 { 268 device_type = "cpu"; 269 compatible = "arm,cortex-a72"; 270 enable-method = "psci"; 271 reg = <0x700>; 272 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 273 d-cache-size = <0x8000>; 274 d-cache-line-size = <64>; 275 d-cache-sets = <128>; 276 i-cache-size = <0xC000>; 277 i-cache-line-size = <64>; 278 i-cache-sets = <192>; 279 next-level-cache = <&cluster7_l2>; 280 cpu-idle-states = <&cpu_pw15>; 281 #cooling-cells = <2>; 282 }; 283 284 cpu701: cpu@701 { 285 device_type = "cpu"; 286 compatible = "arm,cortex-a72"; 287 enable-method = "psci"; 288 reg = <0x701>; 289 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 290 d-cache-size = <0x8000>; 291 d-cache-line-size = <64>; 292 d-cache-sets = <128>; 293 i-cache-size = <0xC000>; 294 i-cache-line-size = <64>; 295 i-cache-sets = <192>; 296 next-level-cache = <&cluster7_l2>; 297 cpu-idle-states = <&cpu_pw15>; 298 #cooling-cells = <2>; 299 }; 300 301 cluster0_l2: l2-cache0 { 302 compatible = "cache"; 303 cache-size = <0x100000>; 304 cache-line-size = <64>; 305 cache-sets = <1024>; 306 cache-level = <2>; 307 }; 308 309 cluster1_l2: l2-cache1 { 310 compatible = "cache"; 311 cache-size = <0x100000>; 312 cache-line-size = <64>; 313 cache-sets = <1024>; 314 cache-level = <2>; 315 }; 316 317 cluster2_l2: l2-cache2 { 318 compatible = "cache"; 319 cache-size = <0x100000>; 320 cache-line-size = <64>; 321 cache-sets = <1024>; 322 cache-level = <2>; 323 }; 324 325 cluster3_l2: l2-cache3 { 326 compatible = "cache"; 327 cache-size = <0x100000>; 328 cache-line-size = <64>; 329 cache-sets = <1024>; 330 cache-level = <2>; 331 }; 332 333 cluster4_l2: l2-cache4 { 334 compatible = "cache"; 335 cache-size = <0x100000>; 336 cache-line-size = <64>; 337 cache-sets = <1024>; 338 cache-level = <2>; 339 }; 340 341 cluster5_l2: l2-cache5 { 342 compatible = "cache"; 343 cache-size = <0x100000>; 344 cache-line-size = <64>; 345 cache-sets = <1024>; 346 cache-level = <2>; 347 }; 348 349 cluster6_l2: l2-cache6 { 350 compatible = "cache"; 351 cache-size = <0x100000>; 352 cache-line-size = <64>; 353 cache-sets = <1024>; 354 cache-level = <2>; 355 }; 356 357 cluster7_l2: l2-cache7 { 358 compatible = "cache"; 359 cache-size = <0x100000>; 360 cache-line-size = <64>; 361 cache-sets = <1024>; 362 cache-level = <2>; 363 }; 364 365 cpu_pw15: cpu-pw15 { 366 compatible = "arm,idle-state"; 367 idle-state-name = "PW15"; 368 arm,psci-suspend-param = <0x0>; 369 entry-latency-us = <2000>; 370 exit-latency-us = <2000>; 371 min-residency-us = <6000>; 372 }; 373 }; 374 375 gic: interrupt-controller@6000000 { 376 compatible = "arm,gic-v3"; 377 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 378 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 379 // SGI_base) 380 <0x0 0x0c0c0000 0 0x2000>, // GICC 381 <0x0 0x0c0d0000 0 0x1000>, // GICH 382 <0x0 0x0c0e0000 0 0x20000>; // GICV 383 #interrupt-cells = <3>; 384 #address-cells = <2>; 385 #size-cells = <2>; 386 ranges; 387 interrupt-controller; 388 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 389 390 its: gic-its@6020000 { 391 compatible = "arm,gic-v3-its"; 392 msi-controller; 393 reg = <0x0 0x6020000 0 0x20000>; 394 }; 395 }; 396 397 timer { 398 compatible = "arm,armv8-timer"; 399 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 403 }; 404 405 pmu { 406 compatible = "arm,cortex-a72-pmu"; 407 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 408 }; 409 410 psci { 411 compatible = "arm,psci-0.2"; 412 method = "smc"; 413 }; 414 415 memory@80000000 { 416 // DRAM space - 1, size : 2 GB DRAM 417 device_type = "memory"; 418 reg = <0x00000000 0x80000000 0 0x80000000>; 419 }; 420 421 ddr1: memory-controller@1080000 { 422 compatible = "fsl,qoriq-memory-controller"; 423 reg = <0x0 0x1080000 0x0 0x1000>; 424 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 425 little-endian; 426 }; 427 428 ddr2: memory-controller@1090000 { 429 compatible = "fsl,qoriq-memory-controller"; 430 reg = <0x0 0x1090000 0x0 0x1000>; 431 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 432 little-endian; 433 }; 434 435 // One clock unit-sysclk node which bootloader require during DT fix-up 436 sysclk: sysclk { 437 compatible = "fixed-clock"; 438 #clock-cells = <0>; 439 clock-frequency = <100000000>; // fixed up by bootloader 440 clock-output-names = "sysclk"; 441 }; 442 443 thermal-zones { 444 cluster6-7 { 445 polling-delay-passive = <1000>; 446 polling-delay = <5000>; 447 thermal-sensors = <&tmu 0>; 448 449 trips { 450 cluster6_7_alert: cluster6-7-alert { 451 temperature = <85000>; 452 hysteresis = <2000>; 453 type = "passive"; 454 }; 455 456 cluster6_7_crit: cluster6-7-crit { 457 temperature = <95000>; 458 hysteresis = <2000>; 459 type = "critical"; 460 }; 461 }; 462 463 cooling-maps { 464 map0 { 465 trip = <&cluster6_7_alert>; 466 cooling-device = 467 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 468 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 469 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 470 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 471 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 472 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 473 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 474 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 475 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 476 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 477 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 478 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 479 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 480 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 481 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 482 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 483 }; 484 }; 485 }; 486 487 ddr-cluster5 { 488 polling-delay-passive = <1000>; 489 polling-delay = <5000>; 490 thermal-sensors = <&tmu 1>; 491 492 trips { 493 ddr-cluster5-alert { 494 temperature = <85000>; 495 hysteresis = <2000>; 496 type = "passive"; 497 }; 498 499 ddr-cluster5-crit { 500 temperature = <95000>; 501 hysteresis = <2000>; 502 type = "critical"; 503 }; 504 }; 505 }; 506 507 wriop { 508 polling-delay-passive = <1000>; 509 polling-delay = <5000>; 510 thermal-sensors = <&tmu 2>; 511 512 trips { 513 wriop-alert { 514 temperature = <85000>; 515 hysteresis = <2000>; 516 type = "passive"; 517 }; 518 519 wriop-crit { 520 temperature = <95000>; 521 hysteresis = <2000>; 522 type = "critical"; 523 }; 524 }; 525 }; 526 527 dce-qbman-hsio2 { 528 polling-delay-passive = <1000>; 529 polling-delay = <5000>; 530 thermal-sensors = <&tmu 3>; 531 532 trips { 533 dce-qbman-alert { 534 temperature = <85000>; 535 hysteresis = <2000>; 536 type = "passive"; 537 }; 538 539 dce-qbman-crit { 540 temperature = <95000>; 541 hysteresis = <2000>; 542 type = "critical"; 543 }; 544 }; 545 }; 546 547 ccn-dpaa-tbu { 548 polling-delay-passive = <1000>; 549 polling-delay = <5000>; 550 thermal-sensors = <&tmu 4>; 551 552 trips { 553 ccn-dpaa-alert { 554 temperature = <85000>; 555 hysteresis = <2000>; 556 type = "passive"; 557 }; 558 559 ccn-dpaa-crit { 560 temperature = <95000>; 561 hysteresis = <2000>; 562 type = "critical"; 563 }; 564 }; 565 }; 566 567 cluster4-hsio3 { 568 polling-delay-passive = <1000>; 569 polling-delay = <5000>; 570 thermal-sensors = <&tmu 5>; 571 572 trips { 573 clust4-hsio3-alert { 574 temperature = <85000>; 575 hysteresis = <2000>; 576 type = "passive"; 577 }; 578 579 clust4-hsio3-crit { 580 temperature = <95000>; 581 hysteresis = <2000>; 582 type = "critical"; 583 }; 584 }; 585 }; 586 587 cluster2-3 { 588 polling-delay-passive = <1000>; 589 polling-delay = <5000>; 590 thermal-sensors = <&tmu 6>; 591 592 trips { 593 cluster2-3-alert { 594 temperature = <85000>; 595 hysteresis = <2000>; 596 type = "passive"; 597 }; 598 599 cluster2-3-crit { 600 temperature = <95000>; 601 hysteresis = <2000>; 602 type = "critical"; 603 }; 604 }; 605 }; 606 }; 607 608 soc { 609 compatible = "simple-bus"; 610 #address-cells = <2>; 611 #size-cells = <2>; 612 ranges; 613 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 614 615 serdes_1: phy@1ea0000 { 616 compatible = "fsl,lynx-28g"; 617 reg = <0x0 0x1ea0000 0x0 0x1e30>; 618 #phy-cells = <1>; 619 }; 620 621 crypto: crypto@8000000 { 622 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 623 fsl,sec-era = <10>; 624 #address-cells = <1>; 625 #size-cells = <1>; 626 ranges = <0x0 0x00 0x8000000 0x100000>; 627 reg = <0x00 0x8000000 0x0 0x100000>; 628 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 629 dma-coherent; 630 status = "disabled"; 631 632 sec_jr0: jr@10000 { 633 compatible = "fsl,sec-v5.0-job-ring", 634 "fsl,sec-v4.0-job-ring"; 635 reg = <0x10000 0x10000>; 636 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 637 }; 638 639 sec_jr1: jr@20000 { 640 compatible = "fsl,sec-v5.0-job-ring", 641 "fsl,sec-v4.0-job-ring"; 642 reg = <0x20000 0x10000>; 643 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 644 }; 645 646 sec_jr2: jr@30000 { 647 compatible = "fsl,sec-v5.0-job-ring", 648 "fsl,sec-v4.0-job-ring"; 649 reg = <0x30000 0x10000>; 650 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 651 }; 652 653 sec_jr3: jr@40000 { 654 compatible = "fsl,sec-v5.0-job-ring", 655 "fsl,sec-v4.0-job-ring"; 656 reg = <0x40000 0x10000>; 657 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 658 }; 659 }; 660 661 clockgen: clock-controller@1300000 { 662 compatible = "fsl,lx2160a-clockgen"; 663 reg = <0 0x1300000 0 0xa0000>; 664 #clock-cells = <2>; 665 clocks = <&sysclk>; 666 }; 667 668 dcfg: syscon@1e00000 { 669 compatible = "fsl,lx2160a-dcfg", "syscon"; 670 reg = <0x0 0x1e00000 0x0 0x10000>; 671 little-endian; 672 }; 673 674 isc: syscon@1f70000 { 675 compatible = "fsl,lx2160a-isc", "syscon"; 676 reg = <0x0 0x1f70000 0x0 0x10000>; 677 little-endian; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 ranges = <0x0 0x0 0x1f70000 0x10000>; 681 682 extirq: interrupt-controller@14 { 683 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; 684 #interrupt-cells = <2>; 685 #address-cells = <0>; 686 interrupt-controller; 687 reg = <0x14 4>; 688 interrupt-map = 689 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 690 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 691 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 692 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 693 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 694 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 695 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 696 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 697 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 698 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 699 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 700 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-map-mask = <0xf 0x0>; 702 }; 703 }; 704 705 tmu: tmu@1f80000 { 706 compatible = "fsl,qoriq-tmu"; 707 reg = <0x0 0x1f80000 0x0 0x10000>; 708 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 709 fsl,tmu-range = <0x800000e6 0x8001017d>; 710 fsl,tmu-calibration = 711 /* Calibration data group 1 */ 712 <0x00000000 0x00000035 713 /* Calibration data group 2 */ 714 0x00000001 0x00000154>; 715 little-endian; 716 #thermal-sensor-cells = <1>; 717 }; 718 719 i2c0: i2c@2000000 { 720 compatible = "fsl,vf610-i2c"; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 reg = <0x0 0x2000000 0x0 0x10000>; 724 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 725 clock-names = "i2c"; 726 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 727 QORIQ_CLK_PLL_DIV(16)>; 728 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 729 status = "disabled"; 730 }; 731 732 i2c1: i2c@2010000 { 733 compatible = "fsl,vf610-i2c"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 reg = <0x0 0x2010000 0x0 0x10000>; 737 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 738 clock-names = "i2c"; 739 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 740 QORIQ_CLK_PLL_DIV(16)>; 741 status = "disabled"; 742 }; 743 744 i2c2: i2c@2020000 { 745 compatible = "fsl,vf610-i2c"; 746 #address-cells = <1>; 747 #size-cells = <0>; 748 reg = <0x0 0x2020000 0x0 0x10000>; 749 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 750 clock-names = "i2c"; 751 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 752 QORIQ_CLK_PLL_DIV(16)>; 753 status = "disabled"; 754 }; 755 756 i2c3: i2c@2030000 { 757 compatible = "fsl,vf610-i2c"; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 reg = <0x0 0x2030000 0x0 0x10000>; 761 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 762 clock-names = "i2c"; 763 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 764 QORIQ_CLK_PLL_DIV(16)>; 765 status = "disabled"; 766 }; 767 768 i2c4: i2c@2040000 { 769 compatible = "fsl,vf610-i2c"; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 reg = <0x0 0x2040000 0x0 0x10000>; 773 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 774 clock-names = "i2c"; 775 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 776 QORIQ_CLK_PLL_DIV(16)>; 777 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 778 status = "disabled"; 779 }; 780 781 i2c5: i2c@2050000 { 782 compatible = "fsl,vf610-i2c"; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 reg = <0x0 0x2050000 0x0 0x10000>; 786 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 787 clock-names = "i2c"; 788 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 789 QORIQ_CLK_PLL_DIV(16)>; 790 status = "disabled"; 791 }; 792 793 i2c6: i2c@2060000 { 794 compatible = "fsl,vf610-i2c"; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 reg = <0x0 0x2060000 0x0 0x10000>; 798 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 799 clock-names = "i2c"; 800 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 801 QORIQ_CLK_PLL_DIV(16)>; 802 status = "disabled"; 803 }; 804 805 i2c7: i2c@2070000 { 806 compatible = "fsl,vf610-i2c"; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 reg = <0x0 0x2070000 0x0 0x10000>; 810 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 811 clock-names = "i2c"; 812 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 813 QORIQ_CLK_PLL_DIV(16)>; 814 status = "disabled"; 815 }; 816 817 fspi: spi@20c0000 { 818 compatible = "nxp,lx2160a-fspi"; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 reg = <0x0 0x20c0000 0x0 0x10000>, 822 <0x0 0x20000000 0x0 0x10000000>; 823 reg-names = "fspi_base", "fspi_mmap"; 824 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 826 QORIQ_CLK_PLL_DIV(4)>, 827 <&clockgen QORIQ_CLK_PLATFORM_PLL 828 QORIQ_CLK_PLL_DIV(4)>; 829 clock-names = "fspi_en", "fspi"; 830 status = "disabled"; 831 }; 832 833 dspi0: spi@2100000 { 834 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 reg = <0x0 0x2100000 0x0 0x10000>; 838 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 840 QORIQ_CLK_PLL_DIV(8)>; 841 clock-names = "dspi"; 842 spi-num-chipselects = <5>; 843 bus-num = <0>; 844 status = "disabled"; 845 }; 846 847 dspi1: spi@2110000 { 848 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 reg = <0x0 0x2110000 0x0 0x10000>; 852 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 854 QORIQ_CLK_PLL_DIV(8)>; 855 clock-names = "dspi"; 856 spi-num-chipselects = <5>; 857 bus-num = <1>; 858 status = "disabled"; 859 }; 860 861 dspi2: spi@2120000 { 862 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 reg = <0x0 0x2120000 0x0 0x10000>; 866 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 868 QORIQ_CLK_PLL_DIV(8)>; 869 clock-names = "dspi"; 870 spi-num-chipselects = <5>; 871 bus-num = <2>; 872 status = "disabled"; 873 }; 874 875 esdhc0: esdhc@2140000 { 876 compatible = "fsl,esdhc"; 877 reg = <0x0 0x2140000 0x0 0x10000>; 878 interrupts = <0 28 0x4>; /* Level high type */ 879 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 880 QORIQ_CLK_PLL_DIV(2)>; 881 dma-coherent; 882 voltage-ranges = <1800 1800 3300 3300>; 883 sdhci,auto-cmd12; 884 little-endian; 885 bus-width = <4>; 886 status = "disabled"; 887 }; 888 889 esdhc1: esdhc@2150000 { 890 compatible = "fsl,esdhc"; 891 reg = <0x0 0x2150000 0x0 0x10000>; 892 interrupts = <0 63 0x4>; /* Level high type */ 893 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 894 QORIQ_CLK_PLL_DIV(2)>; 895 dma-coherent; 896 voltage-ranges = <1800 1800 3300 3300>; 897 sdhci,auto-cmd12; 898 broken-cd; 899 little-endian; 900 bus-width = <4>; 901 status = "disabled"; 902 }; 903 904 can0: can@2180000 { 905 compatible = "fsl,lx2160ar1-flexcan"; 906 reg = <0x0 0x2180000 0x0 0x10000>; 907 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 909 QORIQ_CLK_PLL_DIV(8)>, 910 <&clockgen QORIQ_CLK_SYSCLK 0>; 911 clock-names = "ipg", "per"; 912 fsl,clk-source = /bits/ 8 <0>; 913 status = "disabled"; 914 }; 915 916 can1: can@2190000 { 917 compatible = "fsl,lx2160ar1-flexcan"; 918 reg = <0x0 0x2190000 0x0 0x10000>; 919 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 921 QORIQ_CLK_PLL_DIV(8)>, 922 <&clockgen QORIQ_CLK_SYSCLK 0>; 923 clock-names = "ipg", "per"; 924 fsl,clk-source = /bits/ 8 <0>; 925 status = "disabled"; 926 }; 927 928 uart0: serial@21c0000 { 929 compatible = "arm,sbsa-uart","arm,pl011"; 930 reg = <0x0 0x21c0000 0x0 0x1000>; 931 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 932 current-speed = <115200>; 933 status = "disabled"; 934 }; 935 936 uart1: serial@21d0000 { 937 compatible = "arm,sbsa-uart","arm,pl011"; 938 reg = <0x0 0x21d0000 0x0 0x1000>; 939 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 940 current-speed = <115200>; 941 status = "disabled"; 942 }; 943 944 uart2: serial@21e0000 { 945 compatible = "arm,sbsa-uart","arm,pl011"; 946 reg = <0x0 0x21e0000 0x0 0x1000>; 947 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 948 current-speed = <115200>; 949 status = "disabled"; 950 }; 951 952 uart3: serial@21f0000 { 953 compatible = "arm,sbsa-uart","arm,pl011"; 954 reg = <0x0 0x21f0000 0x0 0x1000>; 955 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 956 current-speed = <115200>; 957 status = "disabled"; 958 }; 959 960 gpio0: gpio@2300000 { 961 compatible = "fsl,qoriq-gpio"; 962 reg = <0x0 0x2300000 0x0 0x10000>; 963 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 964 gpio-controller; 965 little-endian; 966 #gpio-cells = <2>; 967 interrupt-controller; 968 #interrupt-cells = <2>; 969 }; 970 971 gpio1: gpio@2310000 { 972 compatible = "fsl,qoriq-gpio"; 973 reg = <0x0 0x2310000 0x0 0x10000>; 974 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 975 gpio-controller; 976 little-endian; 977 #gpio-cells = <2>; 978 interrupt-controller; 979 #interrupt-cells = <2>; 980 }; 981 982 gpio2: gpio@2320000 { 983 compatible = "fsl,qoriq-gpio"; 984 reg = <0x0 0x2320000 0x0 0x10000>; 985 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 986 gpio-controller; 987 little-endian; 988 #gpio-cells = <2>; 989 interrupt-controller; 990 #interrupt-cells = <2>; 991 }; 992 993 gpio3: gpio@2330000 { 994 compatible = "fsl,qoriq-gpio"; 995 reg = <0x0 0x2330000 0x0 0x10000>; 996 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 997 gpio-controller; 998 little-endian; 999 #gpio-cells = <2>; 1000 interrupt-controller; 1001 #interrupt-cells = <2>; 1002 }; 1003 1004 watchdog@23a0000 { 1005 compatible = "arm,sbsa-gwdt"; 1006 reg = <0x0 0x23a0000 0 0x1000>, 1007 <0x0 0x2390000 0 0x1000>; 1008 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1009 timeout-sec = <30>; 1010 }; 1011 1012 rcpm: power-controller@1e34040 { 1013 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1014 reg = <0x0 0x1e34040 0x0 0x1c>; 1015 #fsl,rcpm-wakeup-cells = <7>; 1016 little-endian; 1017 }; 1018 1019 ftm_alarm0: timer@2800000 { 1020 compatible = "fsl,lx2160a-ftm-alarm"; 1021 reg = <0x0 0x2800000 0x0 0x10000>; 1022 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1023 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1024 }; 1025 1026 usb0: usb@3100000 { 1027 compatible = "snps,dwc3"; 1028 reg = <0x0 0x3100000 0x0 0x10000>; 1029 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1030 dr_mode = "host"; 1031 snps,quirk-frame-length-adjustment = <0x20>; 1032 usb3-lpm-capable; 1033 snps,dis_rxdet_inp3_quirk; 1034 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1035 status = "disabled"; 1036 }; 1037 1038 usb1: usb@3110000 { 1039 compatible = "snps,dwc3"; 1040 reg = <0x0 0x3110000 0x0 0x10000>; 1041 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1042 dr_mode = "host"; 1043 snps,quirk-frame-length-adjustment = <0x20>; 1044 usb3-lpm-capable; 1045 snps,dis_rxdet_inp3_quirk; 1046 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1047 status = "disabled"; 1048 }; 1049 1050 sata0: sata@3200000 { 1051 compatible = "fsl,lx2160a-ahci"; 1052 reg = <0x0 0x3200000 0x0 0x10000>, 1053 <0x7 0x100520 0x0 0x4>; 1054 reg-names = "ahci", "sata-ecc"; 1055 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1057 QORIQ_CLK_PLL_DIV(4)>; 1058 dma-coherent; 1059 status = "disabled"; 1060 }; 1061 1062 sata1: sata@3210000 { 1063 compatible = "fsl,lx2160a-ahci"; 1064 reg = <0x0 0x3210000 0x0 0x10000>, 1065 <0x7 0x100520 0x0 0x4>; 1066 reg-names = "ahci", "sata-ecc"; 1067 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1069 QORIQ_CLK_PLL_DIV(4)>; 1070 dma-coherent; 1071 status = "disabled"; 1072 }; 1073 1074 sata2: sata@3220000 { 1075 compatible = "fsl,lx2160a-ahci"; 1076 reg = <0x0 0x3220000 0x0 0x10000>, 1077 <0x7 0x100520 0x0 0x4>; 1078 reg-names = "ahci", "sata-ecc"; 1079 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1081 QORIQ_CLK_PLL_DIV(4)>; 1082 dma-coherent; 1083 status = "disabled"; 1084 }; 1085 1086 sata3: sata@3230000 { 1087 compatible = "fsl,lx2160a-ahci"; 1088 reg = <0x0 0x3230000 0x0 0x10000>, 1089 <0x7 0x100520 0x0 0x4>; 1090 reg-names = "ahci", "sata-ecc"; 1091 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1093 QORIQ_CLK_PLL_DIV(4)>; 1094 dma-coherent; 1095 status = "disabled"; 1096 }; 1097 1098 pcie1: pcie@3400000 { 1099 compatible = "fsl,lx2160a-pcie"; 1100 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 1101 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 1102 reg-names = "csr_axi_slave", "config_axi_slave"; 1103 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1104 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1105 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1106 interrupt-names = "aer", "pme", "intr"; 1107 #address-cells = <3>; 1108 #size-cells = <2>; 1109 device_type = "pci"; 1110 dma-coherent; 1111 apio-wins = <8>; 1112 ppio-wins = <8>; 1113 bus-range = <0x0 0xff>; 1114 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1115 msi-parent = <&its>; 1116 #interrupt-cells = <1>; 1117 interrupt-map-mask = <0 0 0 7>; 1118 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1119 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1120 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1121 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1122 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1123 status = "disabled"; 1124 }; 1125 1126 pcie2: pcie@3500000 { 1127 compatible = "fsl,lx2160a-pcie"; 1128 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 1129 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 1130 reg-names = "csr_axi_slave", "config_axi_slave"; 1131 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1132 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1133 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1134 interrupt-names = "aer", "pme", "intr"; 1135 #address-cells = <3>; 1136 #size-cells = <2>; 1137 device_type = "pci"; 1138 dma-coherent; 1139 apio-wins = <8>; 1140 ppio-wins = <8>; 1141 bus-range = <0x0 0xff>; 1142 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1143 msi-parent = <&its>; 1144 #interrupt-cells = <1>; 1145 interrupt-map-mask = <0 0 0 7>; 1146 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1147 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1148 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1149 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1150 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1151 status = "disabled"; 1152 }; 1153 1154 pcie3: pcie@3600000 { 1155 compatible = "fsl,lx2160a-pcie"; 1156 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 1157 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 1158 reg-names = "csr_axi_slave", "config_axi_slave"; 1159 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1160 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1161 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1162 interrupt-names = "aer", "pme", "intr"; 1163 #address-cells = <3>; 1164 #size-cells = <2>; 1165 device_type = "pci"; 1166 dma-coherent; 1167 apio-wins = <256>; 1168 ppio-wins = <24>; 1169 bus-range = <0x0 0xff>; 1170 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1171 msi-parent = <&its>; 1172 #interrupt-cells = <1>; 1173 interrupt-map-mask = <0 0 0 7>; 1174 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1175 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1176 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1177 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1178 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1179 status = "disabled"; 1180 }; 1181 1182 pcie4: pcie@3700000 { 1183 compatible = "fsl,lx2160a-pcie"; 1184 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ 1185 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 1186 reg-names = "csr_axi_slave", "config_axi_slave"; 1187 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1188 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1189 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1190 interrupt-names = "aer", "pme", "intr"; 1191 #address-cells = <3>; 1192 #size-cells = <2>; 1193 device_type = "pci"; 1194 dma-coherent; 1195 apio-wins = <8>; 1196 ppio-wins = <8>; 1197 bus-range = <0x0 0xff>; 1198 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1199 msi-parent = <&its>; 1200 #interrupt-cells = <1>; 1201 interrupt-map-mask = <0 0 0 7>; 1202 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1203 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1204 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1205 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1206 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1207 status = "disabled"; 1208 }; 1209 1210 pcie5: pcie@3800000 { 1211 compatible = "fsl,lx2160a-pcie"; 1212 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ 1213 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 1214 reg-names = "csr_axi_slave", "config_axi_slave"; 1215 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1216 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1217 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1218 interrupt-names = "aer", "pme", "intr"; 1219 #address-cells = <3>; 1220 #size-cells = <2>; 1221 device_type = "pci"; 1222 dma-coherent; 1223 apio-wins = <256>; 1224 ppio-wins = <24>; 1225 bus-range = <0x0 0xff>; 1226 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1227 msi-parent = <&its>; 1228 #interrupt-cells = <1>; 1229 interrupt-map-mask = <0 0 0 7>; 1230 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1231 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1232 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1233 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1234 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1235 status = "disabled"; 1236 }; 1237 1238 pcie6: pcie@3900000 { 1239 compatible = "fsl,lx2160a-pcie"; 1240 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ 1241 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 1242 reg-names = "csr_axi_slave", "config_axi_slave"; 1243 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1244 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1245 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1246 interrupt-names = "aer", "pme", "intr"; 1247 #address-cells = <3>; 1248 #size-cells = <2>; 1249 device_type = "pci"; 1250 dma-coherent; 1251 apio-wins = <8>; 1252 ppio-wins = <8>; 1253 bus-range = <0x0 0xff>; 1254 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1255 msi-parent = <&its>; 1256 #interrupt-cells = <1>; 1257 interrupt-map-mask = <0 0 0 7>; 1258 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1259 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1260 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1261 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1262 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1263 status = "disabled"; 1264 }; 1265 1266 smmu: iommu@5000000 { 1267 compatible = "arm,mmu-500"; 1268 reg = <0 0x5000000 0 0x800000>; 1269 #iommu-cells = <1>; 1270 #global-interrupts = <14>; 1271 // global secure fault 1272 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1273 // combined secure 1274 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1275 // global non-secure fault 1276 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1277 // combined non-secure 1278 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1279 // performance counter interrupts 0-9 1280 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1290 // per context interrupt, 64 interrupts 1291 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1355 dma-coherent; 1356 }; 1357 1358 console@8340020 { 1359 compatible = "fsl,dpaa2-console"; 1360 reg = <0x00000000 0x08340020 0 0x2>; 1361 }; 1362 1363 ptp-timer@8b95000 { 1364 compatible = "fsl,dpaa2-ptp"; 1365 reg = <0x0 0x8b95000 0x0 0x100>; 1366 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1367 QORIQ_CLK_PLL_DIV(2)>; 1368 little-endian; 1369 fsl,extts-fifo; 1370 }; 1371 1372 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 1373 emdio1: mdio@8b96000 { 1374 compatible = "fsl,fman-memac-mdio"; 1375 reg = <0x0 0x8b96000 0x0 0x1000>; 1376 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1377 #address-cells = <1>; 1378 #size-cells = <0>; 1379 little-endian; 1380 status = "disabled"; 1381 }; 1382 1383 emdio2: mdio@8b97000 { 1384 compatible = "fsl,fman-memac-mdio"; 1385 reg = <0x0 0x8b97000 0x0 0x1000>; 1386 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1387 little-endian; 1388 #address-cells = <1>; 1389 #size-cells = <0>; 1390 status = "disabled"; 1391 }; 1392 1393 pcs_mdio1: mdio@8c07000 { 1394 compatible = "fsl,fman-memac-mdio"; 1395 reg = <0x0 0x8c07000 0x0 0x1000>; 1396 little-endian; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 status = "disabled"; 1400 1401 pcs1: ethernet-phy@0 { 1402 reg = <0>; 1403 }; 1404 }; 1405 1406 pcs_mdio2: mdio@8c0b000 { 1407 compatible = "fsl,fman-memac-mdio"; 1408 reg = <0x0 0x8c0b000 0x0 0x1000>; 1409 little-endian; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 status = "disabled"; 1413 1414 pcs2: ethernet-phy@0 { 1415 reg = <0>; 1416 }; 1417 }; 1418 1419 pcs_mdio3: mdio@8c0f000 { 1420 compatible = "fsl,fman-memac-mdio"; 1421 reg = <0x0 0x8c0f000 0x0 0x1000>; 1422 little-endian; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 status = "disabled"; 1426 1427 pcs3: ethernet-phy@0 { 1428 reg = <0>; 1429 }; 1430 }; 1431 1432 pcs_mdio4: mdio@8c13000 { 1433 compatible = "fsl,fman-memac-mdio"; 1434 reg = <0x0 0x8c13000 0x0 0x1000>; 1435 little-endian; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 status = "disabled"; 1439 1440 pcs4: ethernet-phy@0 { 1441 reg = <0>; 1442 }; 1443 }; 1444 1445 pcs_mdio5: mdio@8c17000 { 1446 compatible = "fsl,fman-memac-mdio"; 1447 reg = <0x0 0x8c17000 0x0 0x1000>; 1448 little-endian; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 status = "disabled"; 1452 1453 pcs5: ethernet-phy@0 { 1454 reg = <0>; 1455 }; 1456 }; 1457 1458 pcs_mdio6: mdio@8c1b000 { 1459 compatible = "fsl,fman-memac-mdio"; 1460 reg = <0x0 0x8c1b000 0x0 0x1000>; 1461 little-endian; 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 status = "disabled"; 1465 1466 pcs6: ethernet-phy@0 { 1467 reg = <0>; 1468 }; 1469 }; 1470 1471 pcs_mdio7: mdio@8c1f000 { 1472 compatible = "fsl,fman-memac-mdio"; 1473 reg = <0x0 0x8c1f000 0x0 0x1000>; 1474 little-endian; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 status = "disabled"; 1478 1479 pcs7: ethernet-phy@0 { 1480 reg = <0>; 1481 }; 1482 }; 1483 1484 pcs_mdio8: mdio@8c23000 { 1485 compatible = "fsl,fman-memac-mdio"; 1486 reg = <0x0 0x8c23000 0x0 0x1000>; 1487 little-endian; 1488 #address-cells = <1>; 1489 #size-cells = <0>; 1490 status = "disabled"; 1491 1492 pcs8: ethernet-phy@0 { 1493 reg = <0>; 1494 }; 1495 }; 1496 1497 pcs_mdio9: mdio@8c27000 { 1498 compatible = "fsl,fman-memac-mdio"; 1499 reg = <0x0 0x8c27000 0x0 0x1000>; 1500 little-endian; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 status = "disabled"; 1504 1505 pcs9: ethernet-phy@0 { 1506 reg = <0>; 1507 }; 1508 }; 1509 1510 pcs_mdio10: mdio@8c2b000 { 1511 compatible = "fsl,fman-memac-mdio"; 1512 reg = <0x0 0x8c2b000 0x0 0x1000>; 1513 little-endian; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 status = "disabled"; 1517 1518 pcs10: ethernet-phy@0 { 1519 reg = <0>; 1520 }; 1521 }; 1522 1523 pcs_mdio11: mdio@8c2f000 { 1524 compatible = "fsl,fman-memac-mdio"; 1525 reg = <0x0 0x8c2f000 0x0 0x1000>; 1526 little-endian; 1527 #address-cells = <1>; 1528 #size-cells = <0>; 1529 status = "disabled"; 1530 1531 pcs11: ethernet-phy@0 { 1532 reg = <0>; 1533 }; 1534 }; 1535 1536 pcs_mdio12: mdio@8c33000 { 1537 compatible = "fsl,fman-memac-mdio"; 1538 reg = <0x0 0x8c33000 0x0 0x1000>; 1539 little-endian; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 status = "disabled"; 1543 1544 pcs12: ethernet-phy@0 { 1545 reg = <0>; 1546 }; 1547 }; 1548 1549 pcs_mdio13: mdio@8c37000 { 1550 compatible = "fsl,fman-memac-mdio"; 1551 reg = <0x0 0x8c37000 0x0 0x1000>; 1552 little-endian; 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 status = "disabled"; 1556 1557 pcs13: ethernet-phy@0 { 1558 reg = <0>; 1559 }; 1560 }; 1561 1562 pcs_mdio14: mdio@8c3b000 { 1563 compatible = "fsl,fman-memac-mdio"; 1564 reg = <0x0 0x8c3b000 0x0 0x1000>; 1565 little-endian; 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 status = "disabled"; 1569 1570 pcs14: ethernet-phy@0 { 1571 reg = <0>; 1572 }; 1573 }; 1574 1575 pcs_mdio15: mdio@8c3f000 { 1576 compatible = "fsl,fman-memac-mdio"; 1577 reg = <0x0 0x8c3f000 0x0 0x1000>; 1578 little-endian; 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 status = "disabled"; 1582 1583 pcs15: ethernet-phy@0 { 1584 reg = <0>; 1585 }; 1586 }; 1587 1588 pcs_mdio16: mdio@8c43000 { 1589 compatible = "fsl,fman-memac-mdio"; 1590 reg = <0x0 0x8c43000 0x0 0x1000>; 1591 little-endian; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 status = "disabled"; 1595 1596 pcs16: ethernet-phy@0 { 1597 reg = <0>; 1598 }; 1599 }; 1600 1601 pcs_mdio17: mdio@8c47000 { 1602 compatible = "fsl,fman-memac-mdio"; 1603 reg = <0x0 0x8c47000 0x0 0x1000>; 1604 little-endian; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 status = "disabled"; 1608 1609 pcs17: ethernet-phy@0 { 1610 reg = <0>; 1611 }; 1612 }; 1613 1614 pcs_mdio18: mdio@8c4b000 { 1615 compatible = "fsl,fman-memac-mdio"; 1616 reg = <0x0 0x8c4b000 0x0 0x1000>; 1617 little-endian; 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 status = "disabled"; 1621 1622 pcs18: ethernet-phy@0 { 1623 reg = <0>; 1624 }; 1625 }; 1626 1627 fsl_mc: fsl-mc@80c000000 { 1628 compatible = "fsl,qoriq-mc"; 1629 reg = <0x00000008 0x0c000000 0 0x40>, 1630 <0x00000000 0x08340000 0 0x40000>; 1631 msi-parent = <&its>; 1632 /* iommu-map property is fixed up by u-boot */ 1633 iommu-map = <0 &smmu 0 0>; 1634 dma-coherent; 1635 #address-cells = <3>; 1636 #size-cells = <1>; 1637 1638 /* 1639 * Region type 0x0 - MC portals 1640 * Region type 0x1 - QBMAN portals 1641 */ 1642 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1643 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1644 1645 /* 1646 * Define the maximum number of MACs present on the SoC. 1647 */ 1648 dpmacs { 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 1652 dpmac1: ethernet@1 { 1653 compatible = "fsl,qoriq-mc-dpmac"; 1654 reg = <0x1>; 1655 pcs-handle = <&pcs1>; 1656 }; 1657 1658 dpmac2: ethernet@2 { 1659 compatible = "fsl,qoriq-mc-dpmac"; 1660 reg = <0x2>; 1661 pcs-handle = <&pcs2>; 1662 }; 1663 1664 dpmac3: ethernet@3 { 1665 compatible = "fsl,qoriq-mc-dpmac"; 1666 reg = <0x3>; 1667 pcs-handle = <&pcs3>; 1668 }; 1669 1670 dpmac4: ethernet@4 { 1671 compatible = "fsl,qoriq-mc-dpmac"; 1672 reg = <0x4>; 1673 pcs-handle = <&pcs4>; 1674 }; 1675 1676 dpmac5: ethernet@5 { 1677 compatible = "fsl,qoriq-mc-dpmac"; 1678 reg = <0x5>; 1679 pcs-handle = <&pcs5>; 1680 }; 1681 1682 dpmac6: ethernet@6 { 1683 compatible = "fsl,qoriq-mc-dpmac"; 1684 reg = <0x6>; 1685 pcs-handle = <&pcs6>; 1686 }; 1687 1688 dpmac7: ethernet@7 { 1689 compatible = "fsl,qoriq-mc-dpmac"; 1690 reg = <0x7>; 1691 pcs-handle = <&pcs7>; 1692 }; 1693 1694 dpmac8: ethernet@8 { 1695 compatible = "fsl,qoriq-mc-dpmac"; 1696 reg = <0x8>; 1697 pcs-handle = <&pcs8>; 1698 }; 1699 1700 dpmac9: ethernet@9 { 1701 compatible = "fsl,qoriq-mc-dpmac"; 1702 reg = <0x9>; 1703 pcs-handle = <&pcs9>; 1704 }; 1705 1706 dpmac10: ethernet@a { 1707 compatible = "fsl,qoriq-mc-dpmac"; 1708 reg = <0xa>; 1709 pcs-handle = <&pcs10>; 1710 }; 1711 1712 dpmac11: ethernet@b { 1713 compatible = "fsl,qoriq-mc-dpmac"; 1714 reg = <0xb>; 1715 pcs-handle = <&pcs11>; 1716 }; 1717 1718 dpmac12: ethernet@c { 1719 compatible = "fsl,qoriq-mc-dpmac"; 1720 reg = <0xc>; 1721 pcs-handle = <&pcs12>; 1722 }; 1723 1724 dpmac13: ethernet@d { 1725 compatible = "fsl,qoriq-mc-dpmac"; 1726 reg = <0xd>; 1727 pcs-handle = <&pcs13>; 1728 }; 1729 1730 dpmac14: ethernet@e { 1731 compatible = "fsl,qoriq-mc-dpmac"; 1732 reg = <0xe>; 1733 pcs-handle = <&pcs14>; 1734 }; 1735 1736 dpmac15: ethernet@f { 1737 compatible = "fsl,qoriq-mc-dpmac"; 1738 reg = <0xf>; 1739 pcs-handle = <&pcs15>; 1740 }; 1741 1742 dpmac16: ethernet@10 { 1743 compatible = "fsl,qoriq-mc-dpmac"; 1744 reg = <0x10>; 1745 pcs-handle = <&pcs16>; 1746 }; 1747 1748 dpmac17: ethernet@11 { 1749 compatible = "fsl,qoriq-mc-dpmac"; 1750 reg = <0x11>; 1751 pcs-handle = <&pcs17>; 1752 }; 1753 1754 dpmac18: ethernet@12 { 1755 compatible = "fsl,qoriq-mc-dpmac"; 1756 reg = <0x12>; 1757 pcs-handle = <&pcs18>; 1758 }; 1759 }; 1760 }; 1761 }; 1762 1763 firmware { 1764 optee: optee { 1765 compatible = "linaro,optee-tz"; 1766 method = "smc"; 1767 status = "disabled"; 1768 }; 1769 }; 1770}; 1771