1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/memreserve/ 0x80000000 0x00010000; 13 14/ { 15 compatible = "fsl,lx2160a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 rtc1 = &ftm_alarm0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 // 8 clusters having 2 Cortex-A72 cores each 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a72"; 32 enable-method = "psci"; 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 d-cache-size = <0x8000>; 36 d-cache-line-size = <64>; 37 d-cache-sets = <128>; 38 i-cache-size = <0xC000>; 39 i-cache-line-size = <64>; 40 i-cache-sets = <192>; 41 next-level-cache = <&cluster0_l2>; 42 cpu-idle-states = <&cpu_pw15>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a72"; 49 enable-method = "psci"; 50 reg = <0x1>; 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52 d-cache-size = <0x8000>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 i-cache-size = <0xC000>; 56 i-cache-line-size = <64>; 57 i-cache-sets = <192>; 58 next-level-cache = <&cluster0_l2>; 59 cpu-idle-states = <&cpu_pw15>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu100: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a72"; 66 enable-method = "psci"; 67 reg = <0x100>; 68 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 69 d-cache-size = <0x8000>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 i-cache-size = <0xC000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <192>; 75 next-level-cache = <&cluster1_l2>; 76 cpu-idle-states = <&cpu_pw15>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu101: cpu@101 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a72"; 83 enable-method = "psci"; 84 reg = <0x101>; 85 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 86 d-cache-size = <0x8000>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 i-cache-size = <0xC000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <192>; 92 next-level-cache = <&cluster1_l2>; 93 cpu-idle-states = <&cpu_pw15>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu200: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a72"; 100 enable-method = "psci"; 101 reg = <0x200>; 102 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 103 d-cache-size = <0x8000>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 i-cache-size = <0xC000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <192>; 109 next-level-cache = <&cluster2_l2>; 110 cpu-idle-states = <&cpu_pw15>; 111 #cooling-cells = <2>; 112 }; 113 114 cpu201: cpu@201 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a72"; 117 enable-method = "psci"; 118 reg = <0x201>; 119 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 120 d-cache-size = <0x8000>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <128>; 123 i-cache-size = <0xC000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <192>; 126 next-level-cache = <&cluster2_l2>; 127 cpu-idle-states = <&cpu_pw15>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu300: cpu@300 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a72"; 134 enable-method = "psci"; 135 reg = <0x300>; 136 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 137 d-cache-size = <0x8000>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <128>; 140 i-cache-size = <0xC000>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <192>; 143 next-level-cache = <&cluster3_l2>; 144 cpu-idle-states = <&cpu_pw15>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu301: cpu@301 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a72"; 151 enable-method = "psci"; 152 reg = <0x301>; 153 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 154 d-cache-size = <0x8000>; 155 d-cache-line-size = <64>; 156 d-cache-sets = <128>; 157 i-cache-size = <0xC000>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <192>; 160 next-level-cache = <&cluster3_l2>; 161 cpu-idle-states = <&cpu_pw15>; 162 #cooling-cells = <2>; 163 }; 164 165 cpu400: cpu@400 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a72"; 168 enable-method = "psci"; 169 reg = <0x400>; 170 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 i-cache-size = <0xC000>; 175 i-cache-line-size = <64>; 176 i-cache-sets = <192>; 177 next-level-cache = <&cluster4_l2>; 178 cpu-idle-states = <&cpu_pw15>; 179 #cooling-cells = <2>; 180 }; 181 182 cpu401: cpu@401 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a72"; 185 enable-method = "psci"; 186 reg = <0x401>; 187 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 188 d-cache-size = <0x8000>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <128>; 191 i-cache-size = <0xC000>; 192 i-cache-line-size = <64>; 193 i-cache-sets = <192>; 194 next-level-cache = <&cluster4_l2>; 195 cpu-idle-states = <&cpu_pw15>; 196 #cooling-cells = <2>; 197 }; 198 199 cpu500: cpu@500 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a72"; 202 enable-method = "psci"; 203 reg = <0x500>; 204 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 205 d-cache-size = <0x8000>; 206 d-cache-line-size = <64>; 207 d-cache-sets = <128>; 208 i-cache-size = <0xC000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <192>; 211 next-level-cache = <&cluster5_l2>; 212 cpu-idle-states = <&cpu_pw15>; 213 #cooling-cells = <2>; 214 }; 215 216 cpu501: cpu@501 { 217 device_type = "cpu"; 218 compatible = "arm,cortex-a72"; 219 enable-method = "psci"; 220 reg = <0x501>; 221 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 222 d-cache-size = <0x8000>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <128>; 225 i-cache-size = <0xC000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <192>; 228 next-level-cache = <&cluster5_l2>; 229 cpu-idle-states = <&cpu_pw15>; 230 #cooling-cells = <2>; 231 }; 232 233 cpu600: cpu@600 { 234 device_type = "cpu"; 235 compatible = "arm,cortex-a72"; 236 enable-method = "psci"; 237 reg = <0x600>; 238 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 239 d-cache-size = <0x8000>; 240 d-cache-line-size = <64>; 241 d-cache-sets = <128>; 242 i-cache-size = <0xC000>; 243 i-cache-line-size = <64>; 244 i-cache-sets = <192>; 245 next-level-cache = <&cluster6_l2>; 246 cpu-idle-states = <&cpu_pw15>; 247 #cooling-cells = <2>; 248 }; 249 250 cpu601: cpu@601 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 enable-method = "psci"; 254 reg = <0x601>; 255 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 256 d-cache-size = <0x8000>; 257 d-cache-line-size = <64>; 258 d-cache-sets = <128>; 259 i-cache-size = <0xC000>; 260 i-cache-line-size = <64>; 261 i-cache-sets = <192>; 262 next-level-cache = <&cluster6_l2>; 263 cpu-idle-states = <&cpu_pw15>; 264 #cooling-cells = <2>; 265 }; 266 267 cpu700: cpu@700 { 268 device_type = "cpu"; 269 compatible = "arm,cortex-a72"; 270 enable-method = "psci"; 271 reg = <0x700>; 272 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 273 d-cache-size = <0x8000>; 274 d-cache-line-size = <64>; 275 d-cache-sets = <128>; 276 i-cache-size = <0xC000>; 277 i-cache-line-size = <64>; 278 i-cache-sets = <192>; 279 next-level-cache = <&cluster7_l2>; 280 cpu-idle-states = <&cpu_pw15>; 281 #cooling-cells = <2>; 282 }; 283 284 cpu701: cpu@701 { 285 device_type = "cpu"; 286 compatible = "arm,cortex-a72"; 287 enable-method = "psci"; 288 reg = <0x701>; 289 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 290 d-cache-size = <0x8000>; 291 d-cache-line-size = <64>; 292 d-cache-sets = <128>; 293 i-cache-size = <0xC000>; 294 i-cache-line-size = <64>; 295 i-cache-sets = <192>; 296 next-level-cache = <&cluster7_l2>; 297 cpu-idle-states = <&cpu_pw15>; 298 #cooling-cells = <2>; 299 }; 300 301 cluster0_l2: l2-cache0 { 302 compatible = "cache"; 303 cache-unified; 304 cache-size = <0x100000>; 305 cache-line-size = <64>; 306 cache-sets = <1024>; 307 cache-level = <2>; 308 }; 309 310 cluster1_l2: l2-cache1 { 311 compatible = "cache"; 312 cache-unified; 313 cache-size = <0x100000>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 }; 318 319 cluster2_l2: l2-cache2 { 320 compatible = "cache"; 321 cache-unified; 322 cache-size = <0x100000>; 323 cache-line-size = <64>; 324 cache-sets = <1024>; 325 cache-level = <2>; 326 }; 327 328 cluster3_l2: l2-cache3 { 329 compatible = "cache"; 330 cache-unified; 331 cache-size = <0x100000>; 332 cache-line-size = <64>; 333 cache-sets = <1024>; 334 cache-level = <2>; 335 }; 336 337 cluster4_l2: l2-cache4 { 338 compatible = "cache"; 339 cache-unified; 340 cache-size = <0x100000>; 341 cache-line-size = <64>; 342 cache-sets = <1024>; 343 cache-level = <2>; 344 }; 345 346 cluster5_l2: l2-cache5 { 347 compatible = "cache"; 348 cache-unified; 349 cache-size = <0x100000>; 350 cache-line-size = <64>; 351 cache-sets = <1024>; 352 cache-level = <2>; 353 }; 354 355 cluster6_l2: l2-cache6 { 356 compatible = "cache"; 357 cache-unified; 358 cache-size = <0x100000>; 359 cache-line-size = <64>; 360 cache-sets = <1024>; 361 cache-level = <2>; 362 }; 363 364 cluster7_l2: l2-cache7 { 365 compatible = "cache"; 366 cache-unified; 367 cache-size = <0x100000>; 368 cache-line-size = <64>; 369 cache-sets = <1024>; 370 cache-level = <2>; 371 }; 372 373 cpu_pw15: cpu-pw15 { 374 compatible = "arm,idle-state"; 375 idle-state-name = "PW15"; 376 arm,psci-suspend-param = <0x0>; 377 entry-latency-us = <2000>; 378 exit-latency-us = <2000>; 379 min-residency-us = <6000>; 380 }; 381 }; 382 383 gic: interrupt-controller@6000000 { 384 compatible = "arm,gic-v3"; 385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 387 // SGI_base) 388 <0x0 0x0c0c0000 0 0x2000>, // GICC 389 <0x0 0x0c0d0000 0 0x1000>, // GICH 390 <0x0 0x0c0e0000 0 0x20000>; // GICV 391 #interrupt-cells = <3>; 392 #address-cells = <2>; 393 #size-cells = <2>; 394 ranges; 395 interrupt-controller; 396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 397 398 its: msi-controller@6020000 { 399 compatible = "arm,gic-v3-its"; 400 msi-controller; 401 reg = <0x0 0x6020000 0 0x20000>; 402 }; 403 }; 404 405 timer { 406 compatible = "arm,armv8-timer"; 407 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 411 }; 412 413 pmu { 414 compatible = "arm,cortex-a72-pmu"; 415 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 416 }; 417 418 psci { 419 compatible = "arm,psci-0.2"; 420 method = "smc"; 421 }; 422 423 memory@80000000 { 424 // DRAM space - 1, size : 2 GB DRAM 425 device_type = "memory"; 426 reg = <0x00000000 0x80000000 0 0x80000000>; 427 }; 428 429 ddr1: memory-controller@1080000 { 430 compatible = "fsl,qoriq-memory-controller"; 431 reg = <0x0 0x1080000 0x0 0x1000>; 432 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 433 little-endian; 434 }; 435 436 ddr2: memory-controller@1090000 { 437 compatible = "fsl,qoriq-memory-controller"; 438 reg = <0x0 0x1090000 0x0 0x1000>; 439 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 440 little-endian; 441 }; 442 443 // One clock unit-sysclk node which bootloader require during DT fix-up 444 sysclk: sysclk { 445 compatible = "fixed-clock"; 446 #clock-cells = <0>; 447 clock-frequency = <100000000>; // fixed up by bootloader 448 clock-output-names = "sysclk"; 449 }; 450 451 thermal-zones { 452 cluster6-7-thermal { 453 polling-delay-passive = <1000>; 454 polling-delay = <5000>; 455 thermal-sensors = <&tmu 0>; 456 457 trips { 458 cluster6_7_alert: cluster6-7-alert { 459 temperature = <85000>; 460 hysteresis = <2000>; 461 type = "passive"; 462 }; 463 464 cluster6_7_crit: cluster6-7-crit { 465 temperature = <95000>; 466 hysteresis = <2000>; 467 type = "critical"; 468 }; 469 }; 470 471 cooling-maps { 472 map0 { 473 trip = <&cluster6_7_alert>; 474 cooling-device = 475 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 476 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 477 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 478 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 479 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 480 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 481 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 482 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 483 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 484 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 485 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 486 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 487 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 488 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 489 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 490 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 491 }; 492 }; 493 }; 494 495 ddr-ctrl5-thermal { 496 polling-delay-passive = <1000>; 497 polling-delay = <5000>; 498 thermal-sensors = <&tmu 1>; 499 500 trips { 501 ddr-cluster5-alert { 502 temperature = <85000>; 503 hysteresis = <2000>; 504 type = "passive"; 505 }; 506 507 ddr-cluster5-crit { 508 temperature = <95000>; 509 hysteresis = <2000>; 510 type = "critical"; 511 }; 512 }; 513 }; 514 515 wriop-thermal { 516 polling-delay-passive = <1000>; 517 polling-delay = <5000>; 518 thermal-sensors = <&tmu 2>; 519 520 trips { 521 wriop-alert { 522 temperature = <85000>; 523 hysteresis = <2000>; 524 type = "passive"; 525 }; 526 527 wriop-crit { 528 temperature = <95000>; 529 hysteresis = <2000>; 530 type = "critical"; 531 }; 532 }; 533 }; 534 535 dce-thermal { 536 polling-delay-passive = <1000>; 537 polling-delay = <5000>; 538 thermal-sensors = <&tmu 3>; 539 540 trips { 541 dce-qbman-alert { 542 temperature = <85000>; 543 hysteresis = <2000>; 544 type = "passive"; 545 }; 546 547 dce-qbman-crit { 548 temperature = <95000>; 549 hysteresis = <2000>; 550 type = "critical"; 551 }; 552 }; 553 }; 554 555 ccn-thermal { 556 polling-delay-passive = <1000>; 557 polling-delay = <5000>; 558 thermal-sensors = <&tmu 4>; 559 560 trips { 561 ccn-dpaa-alert { 562 temperature = <85000>; 563 hysteresis = <2000>; 564 type = "passive"; 565 }; 566 567 ccn-dpaa-crit { 568 temperature = <95000>; 569 hysteresis = <2000>; 570 type = "critical"; 571 }; 572 }; 573 }; 574 575 cluster4-thermal { 576 polling-delay-passive = <1000>; 577 polling-delay = <5000>; 578 thermal-sensors = <&tmu 5>; 579 580 trips { 581 clust4-hsio3-alert { 582 temperature = <85000>; 583 hysteresis = <2000>; 584 type = "passive"; 585 }; 586 587 clust4-hsio3-crit { 588 temperature = <95000>; 589 hysteresis = <2000>; 590 type = "critical"; 591 }; 592 }; 593 }; 594 595 cluster2-3-thermal { 596 polling-delay-passive = <1000>; 597 polling-delay = <5000>; 598 thermal-sensors = <&tmu 6>; 599 600 trips { 601 cluster2-3-alert { 602 temperature = <85000>; 603 hysteresis = <2000>; 604 type = "passive"; 605 }; 606 607 cluster2-3-crit { 608 temperature = <95000>; 609 hysteresis = <2000>; 610 type = "critical"; 611 }; 612 }; 613 }; 614 }; 615 616 soc { 617 compatible = "simple-bus"; 618 #address-cells = <2>; 619 #size-cells = <2>; 620 ranges; 621 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 622 623 serdes_1: phy@1ea0000 { 624 compatible = "fsl,lynx-28g"; 625 reg = <0x0 0x1ea0000 0x0 0x1e30>; 626 #phy-cells = <1>; 627 }; 628 629 serdes_2: phy@1eb0000 { 630 compatible = "fsl,lynx-28g"; 631 reg = <0x0 0x1eb0000 0x0 0x1e30>; 632 #phy-cells = <1>; 633 status = "disabled"; 634 }; 635 636 crypto: crypto@8000000 { 637 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 638 fsl,sec-era = <10>; 639 #address-cells = <1>; 640 #size-cells = <1>; 641 ranges = <0x0 0x00 0x8000000 0x100000>; 642 reg = <0x00 0x8000000 0x0 0x100000>; 643 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 644 dma-coherent; 645 status = "disabled"; 646 647 sec_jr0: jr@10000 { 648 compatible = "fsl,sec-v5.0-job-ring", 649 "fsl,sec-v4.0-job-ring"; 650 reg = <0x10000 0x10000>; 651 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 652 }; 653 654 sec_jr1: jr@20000 { 655 compatible = "fsl,sec-v5.0-job-ring", 656 "fsl,sec-v4.0-job-ring"; 657 reg = <0x20000 0x10000>; 658 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 659 }; 660 661 sec_jr2: jr@30000 { 662 compatible = "fsl,sec-v5.0-job-ring", 663 "fsl,sec-v4.0-job-ring"; 664 reg = <0x30000 0x10000>; 665 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 666 }; 667 668 sec_jr3: jr@40000 { 669 compatible = "fsl,sec-v5.0-job-ring", 670 "fsl,sec-v4.0-job-ring"; 671 reg = <0x40000 0x10000>; 672 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 673 }; 674 }; 675 676 clockgen: clock-controller@1300000 { 677 compatible = "fsl,lx2160a-clockgen"; 678 reg = <0 0x1300000 0 0xa0000>; 679 #clock-cells = <2>; 680 clocks = <&sysclk>; 681 }; 682 683 dcfg: syscon@1e00000 { 684 compatible = "fsl,lx2160a-dcfg", "syscon"; 685 reg = <0x0 0x1e00000 0x0 0x10000>; 686 little-endian; 687 }; 688 689 sfp: efuse@1e80000 { 690 compatible = "fsl,ls1028a-sfp"; 691 reg = <0x0 0x1e80000 0x0 0x10000>; 692 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 693 QORIQ_CLK_PLL_DIV(4)>; 694 clock-names = "sfp"; 695 }; 696 697 isc: syscon@1f70000 { 698 compatible = "fsl,lx2160a-isc", "syscon"; 699 reg = <0x0 0x1f70000 0x0 0x10000>; 700 little-endian; 701 #address-cells = <1>; 702 #size-cells = <1>; 703 ranges = <0x0 0x0 0x1f70000 0x10000>; 704 705 extirq: interrupt-controller@14 { 706 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; 707 #interrupt-cells = <2>; 708 #address-cells = <0>; 709 interrupt-controller; 710 reg = <0x14 4>; 711 interrupt-map = 712 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 713 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 714 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 715 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 716 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 717 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 718 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 719 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 720 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 721 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 722 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 723 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 724 interrupt-map-mask = <0xf 0x0>; 725 }; 726 }; 727 728 tmu: tmu@1f80000 { 729 compatible = "fsl,qoriq-tmu"; 730 reg = <0x0 0x1f80000 0x0 0x10000>; 731 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 732 fsl,tmu-range = <0x800000e6 0x8001017d>; 733 fsl,tmu-calibration = 734 /* Calibration data group 1 */ 735 <0x00000000 0x00000035>, 736 /* Calibration data group 2 */ 737 <0x00000001 0x00000154>; 738 little-endian; 739 #thermal-sensor-cells = <1>; 740 }; 741 742 i2c0: i2c@2000000 { 743 compatible = "fsl,vf610-i2c"; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 reg = <0x0 0x2000000 0x0 0x10000>; 747 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 748 clock-names = "ipg"; 749 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 750 QORIQ_CLK_PLL_DIV(16)>; 751 pinctrl-names = "default", "gpio"; 752 pinctrl-0 = <&i2c0_scl>; 753 pinctrl-1 = <&i2c0_scl_gpio>; 754 scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 755 status = "disabled"; 756 }; 757 758 i2c1: i2c@2010000 { 759 compatible = "fsl,vf610-i2c"; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 reg = <0x0 0x2010000 0x0 0x10000>; 763 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 764 clock-names = "ipg"; 765 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 766 QORIQ_CLK_PLL_DIV(16)>; 767 pinctrl-names = "default", "gpio"; 768 pinctrl-0 = <&i2c1_scl>; 769 pinctrl-1 = <&i2c1_scl_gpio>; 770 scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 771 status = "disabled"; 772 }; 773 774 i2c2: i2c@2020000 { 775 compatible = "fsl,vf610-i2c"; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 reg = <0x0 0x2020000 0x0 0x10000>; 779 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 780 clock-names = "ipg"; 781 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 782 QORIQ_CLK_PLL_DIV(16)>; 783 pinctrl-names = "default", "gpio"; 784 pinctrl-0 = <&i2c2_scl>; 785 pinctrl-1 = <&i2c2_scl_gpio>; 786 scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 787 status = "disabled"; 788 }; 789 790 i2c3: i2c@2030000 { 791 compatible = "fsl,vf610-i2c"; 792 #address-cells = <1>; 793 #size-cells = <0>; 794 reg = <0x0 0x2030000 0x0 0x10000>; 795 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 796 clock-names = "ipg"; 797 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 798 QORIQ_CLK_PLL_DIV(16)>; 799 pinctrl-names = "default", "gpio"; 800 pinctrl-0 = <&i2c3_scl>; 801 pinctrl-1 = <&i2c3_scl_gpio>; 802 scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 803 status = "disabled"; 804 }; 805 806 i2c4: i2c@2040000 { 807 compatible = "fsl,vf610-i2c"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 reg = <0x0 0x2040000 0x0 0x10000>; 811 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 812 clock-names = "ipg"; 813 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 814 QORIQ_CLK_PLL_DIV(16)>; 815 pinctrl-names = "default", "gpio"; 816 pinctrl-0 = <&i2c4_scl>; 817 pinctrl-1 = <&i2c4_scl_gpio>; 818 scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 819 status = "disabled"; 820 }; 821 822 i2c5: i2c@2050000 { 823 compatible = "fsl,vf610-i2c"; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 reg = <0x0 0x2050000 0x0 0x10000>; 827 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 828 clock-names = "ipg"; 829 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 830 QORIQ_CLK_PLL_DIV(16)>; 831 pinctrl-names = "default", "gpio"; 832 pinctrl-0 = <&i2c5_scl>; 833 pinctrl-1 = <&i2c5_scl_gpio>; 834 scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 835 status = "disabled"; 836 }; 837 838 i2c6: i2c@2060000 { 839 compatible = "fsl,vf610-i2c"; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 reg = <0x0 0x2060000 0x0 0x10000>; 843 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 844 clock-names = "ipg"; 845 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 846 QORIQ_CLK_PLL_DIV(16)>; 847 pinctrl-names = "default", "gpio"; 848 pinctrl-0 = <&i2c6_scl>; 849 pinctrl-1 = <&i2c6_scl_gpio>; 850 scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 851 status = "disabled"; 852 }; 853 854 i2c7: i2c@2070000 { 855 compatible = "fsl,vf610-i2c"; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 reg = <0x0 0x2070000 0x0 0x10000>; 859 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 860 clock-names = "ipg"; 861 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 862 QORIQ_CLK_PLL_DIV(16)>; 863 pinctrl-names = "default", "gpio"; 864 pinctrl-0 = <&i2c7_scl>; 865 pinctrl-1 = <&i2c7_scl_gpio>; 866 scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 867 status = "disabled"; 868 }; 869 870 fspi: spi@20c0000 { 871 compatible = "nxp,lx2160a-fspi"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 reg = <0x0 0x20c0000 0x0 0x10000>, 875 <0x0 0x20000000 0x0 0x10000000>; 876 reg-names = "fspi_base", "fspi_mmap"; 877 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 879 QORIQ_CLK_PLL_DIV(4)>, 880 <&clockgen QORIQ_CLK_PLATFORM_PLL 881 QORIQ_CLK_PLL_DIV(4)>; 882 clock-names = "fspi_en", "fspi"; 883 status = "disabled"; 884 }; 885 886 dspi0: spi@2100000 { 887 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 reg = <0x0 0x2100000 0x0 0x10000>; 891 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 893 QORIQ_CLK_PLL_DIV(8)>; 894 clock-names = "dspi"; 895 spi-num-chipselects = <5>; 896 bus-num = <0>; 897 status = "disabled"; 898 }; 899 900 dspi1: spi@2110000 { 901 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 reg = <0x0 0x2110000 0x0 0x10000>; 905 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 907 QORIQ_CLK_PLL_DIV(8)>; 908 clock-names = "dspi"; 909 spi-num-chipselects = <5>; 910 bus-num = <1>; 911 status = "disabled"; 912 }; 913 914 dspi2: spi@2120000 { 915 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 reg = <0x0 0x2120000 0x0 0x10000>; 919 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 920 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 921 QORIQ_CLK_PLL_DIV(8)>; 922 clock-names = "dspi"; 923 spi-num-chipselects = <5>; 924 bus-num = <2>; 925 status = "disabled"; 926 }; 927 928 esdhc0: mmc@2140000 { 929 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 930 reg = <0x0 0x2140000 0x0 0x10000>; 931 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 933 QORIQ_CLK_PLL_DIV(2)>; 934 dma-coherent; 935 voltage-ranges = <1800 1800 3300 3300>; 936 sdhci,auto-cmd12; 937 little-endian; 938 bus-width = <4>; 939 status = "disabled"; 940 }; 941 942 esdhc1: mmc@2150000 { 943 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 944 reg = <0x0 0x2150000 0x0 0x10000>; 945 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 947 QORIQ_CLK_PLL_DIV(2)>; 948 dma-coherent; 949 voltage-ranges = <1800 1800 3300 3300>; 950 sdhci,auto-cmd12; 951 broken-cd; 952 little-endian; 953 bus-width = <4>; 954 status = "disabled"; 955 }; 956 957 can0: can@2180000 { 958 compatible = "fsl,lx2160ar1-flexcan"; 959 reg = <0x0 0x2180000 0x0 0x10000>; 960 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 962 QORIQ_CLK_PLL_DIV(8)>, 963 <&clockgen QORIQ_CLK_SYSCLK 0>; 964 clock-names = "ipg", "per"; 965 fsl,clk-source = /bits/ 8 <0>; 966 status = "disabled"; 967 }; 968 969 can1: can@2190000 { 970 compatible = "fsl,lx2160ar1-flexcan"; 971 reg = <0x0 0x2190000 0x0 0x10000>; 972 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 974 QORIQ_CLK_PLL_DIV(8)>, 975 <&clockgen QORIQ_CLK_SYSCLK 0>; 976 clock-names = "ipg", "per"; 977 fsl,clk-source = /bits/ 8 <0>; 978 status = "disabled"; 979 }; 980 981 uart0: serial@21c0000 { 982 compatible = "arm,pl011", "arm,primecell"; 983 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 984 QORIQ_CLK_PLL_DIV(8)>, 985 <&clockgen QORIQ_CLK_PLATFORM_PLL 986 QORIQ_CLK_PLL_DIV(8)>; 987 clock-names = "uartclk", "apb_pclk"; 988 reg = <0x0 0x21c0000 0x0 0x1000>; 989 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 990 status = "disabled"; 991 }; 992 993 uart1: serial@21d0000 { 994 compatible = "arm,pl011", "arm,primecell"; 995 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 996 QORIQ_CLK_PLL_DIV(8)>, 997 <&clockgen QORIQ_CLK_PLATFORM_PLL 998 QORIQ_CLK_PLL_DIV(8)>; 999 clock-names = "uartclk", "apb_pclk"; 1000 reg = <0x0 0x21d0000 0x0 0x1000>; 1001 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1002 status = "disabled"; 1003 }; 1004 1005 uart2: serial@21e0000 { 1006 compatible = "arm,pl011", "arm,primecell"; 1007 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1008 QORIQ_CLK_PLL_DIV(8)>, 1009 <&clockgen QORIQ_CLK_PLATFORM_PLL 1010 QORIQ_CLK_PLL_DIV(8)>; 1011 clock-names = "uartclk", "apb_pclk"; 1012 reg = <0x0 0x21e0000 0x0 0x1000>; 1013 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1014 status = "disabled"; 1015 }; 1016 1017 uart3: serial@21f0000 { 1018 compatible = "arm,pl011", "arm,primecell"; 1019 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1020 QORIQ_CLK_PLL_DIV(8)>, 1021 <&clockgen QORIQ_CLK_PLATFORM_PLL 1022 QORIQ_CLK_PLL_DIV(8)>; 1023 clock-names = "uartclk", "apb_pclk"; 1024 reg = <0x0 0x21f0000 0x0 0x1000>; 1025 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1026 status = "disabled"; 1027 }; 1028 1029 gpio0: gpio@2300000 { 1030 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1031 reg = <0x0 0x2300000 0x0 0x10000>; 1032 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1033 gpio-controller; 1034 little-endian; 1035 #gpio-cells = <2>; 1036 interrupt-controller; 1037 #interrupt-cells = <2>; 1038 }; 1039 1040 gpio1: gpio@2310000 { 1041 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1042 reg = <0x0 0x2310000 0x0 0x10000>; 1043 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1044 gpio-controller; 1045 little-endian; 1046 #gpio-cells = <2>; 1047 interrupt-controller; 1048 #interrupt-cells = <2>; 1049 }; 1050 1051 gpio2: gpio@2320000 { 1052 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1053 reg = <0x0 0x2320000 0x0 0x10000>; 1054 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1055 gpio-controller; 1056 little-endian; 1057 #gpio-cells = <2>; 1058 interrupt-controller; 1059 #interrupt-cells = <2>; 1060 }; 1061 1062 gpio3: gpio@2330000 { 1063 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1064 reg = <0x0 0x2330000 0x0 0x10000>; 1065 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1066 gpio-controller; 1067 little-endian; 1068 #gpio-cells = <2>; 1069 interrupt-controller; 1070 #interrupt-cells = <2>; 1071 }; 1072 1073 watchdog@23a0000 { 1074 compatible = "arm,sbsa-gwdt"; 1075 reg = <0x0 0x23a0000 0 0x1000>, 1076 <0x0 0x2390000 0 0x1000>; 1077 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1078 timeout-sec = <30>; 1079 }; 1080 1081 rcpm: power-controller@1e34040 { 1082 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1083 reg = <0x0 0x1e34040 0x0 0x1c>; 1084 #fsl,rcpm-wakeup-cells = <7>; 1085 little-endian; 1086 }; 1087 1088 ftm_alarm0: rtc@2800000 { 1089 compatible = "fsl,lx2160a-ftm-alarm"; 1090 reg = <0x0 0x2800000 0x0 0x10000>; 1091 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1092 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1093 }; 1094 1095 usb0: usb@3100000 { 1096 compatible = "snps,dwc3"; 1097 reg = <0x0 0x3100000 0x0 0x10000>; 1098 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1099 dr_mode = "host"; 1100 snps,quirk-frame-length-adjustment = <0x20>; 1101 usb3-lpm-capable; 1102 snps,dis_rxdet_inp3_quirk; 1103 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1104 status = "disabled"; 1105 }; 1106 1107 usb1: usb@3110000 { 1108 compatible = "snps,dwc3"; 1109 reg = <0x0 0x3110000 0x0 0x10000>; 1110 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1111 dr_mode = "host"; 1112 snps,quirk-frame-length-adjustment = <0x20>; 1113 usb3-lpm-capable; 1114 snps,dis_rxdet_inp3_quirk; 1115 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1116 status = "disabled"; 1117 }; 1118 1119 sata0: sata@3200000 { 1120 compatible = "fsl,lx2160a-ahci"; 1121 reg = <0x0 0x3200000 0x0 0x10000>, 1122 <0x7 0x100520 0x0 0x4>; 1123 reg-names = "ahci", "sata-ecc"; 1124 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1126 QORIQ_CLK_PLL_DIV(4)>; 1127 dma-coherent; 1128 status = "disabled"; 1129 }; 1130 1131 sata1: sata@3210000 { 1132 compatible = "fsl,lx2160a-ahci"; 1133 reg = <0x0 0x3210000 0x0 0x10000>, 1134 <0x7 0x100520 0x0 0x4>; 1135 reg-names = "ahci", "sata-ecc"; 1136 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1138 QORIQ_CLK_PLL_DIV(4)>; 1139 dma-coherent; 1140 status = "disabled"; 1141 }; 1142 1143 sata2: sata@3220000 { 1144 compatible = "fsl,lx2160a-ahci"; 1145 reg = <0x0 0x3220000 0x0 0x10000>, 1146 <0x7 0x100520 0x0 0x4>; 1147 reg-names = "ahci", "sata-ecc"; 1148 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1150 QORIQ_CLK_PLL_DIV(4)>; 1151 dma-coherent; 1152 status = "disabled"; 1153 }; 1154 1155 sata3: sata@3230000 { 1156 compatible = "fsl,lx2160a-ahci"; 1157 reg = <0x0 0x3230000 0x0 0x10000>, 1158 <0x7 0x100520 0x0 0x4>; 1159 reg-names = "ahci", "sata-ecc"; 1160 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1162 QORIQ_CLK_PLL_DIV(4)>; 1163 dma-coherent; 1164 status = "disabled"; 1165 }; 1166 1167 pcie1: pcie@3400000 { 1168 compatible = "fsl,lx2160a-pcie"; 1169 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 1170 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 1171 reg-names = "csr_axi_slave", "config_axi_slave"; 1172 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1173 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1174 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1175 interrupt-names = "aer", "pme", "intr"; 1176 #address-cells = <3>; 1177 #size-cells = <2>; 1178 device_type = "pci"; 1179 dma-coherent; 1180 apio-wins = <8>; 1181 ppio-wins = <8>; 1182 bus-range = <0x0 0xff>; 1183 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1184 msi-parent = <&its>; 1185 #interrupt-cells = <1>; 1186 interrupt-map-mask = <0 0 0 7>; 1187 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1188 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1189 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1190 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1191 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1192 status = "disabled"; 1193 }; 1194 1195 pcie2: pcie@3500000 { 1196 compatible = "fsl,lx2160a-pcie"; 1197 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 1198 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 1199 reg-names = "csr_axi_slave", "config_axi_slave"; 1200 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1201 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1202 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1203 interrupt-names = "aer", "pme", "intr"; 1204 #address-cells = <3>; 1205 #size-cells = <2>; 1206 device_type = "pci"; 1207 dma-coherent; 1208 apio-wins = <8>; 1209 ppio-wins = <8>; 1210 bus-range = <0x0 0xff>; 1211 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1212 msi-parent = <&its>; 1213 #interrupt-cells = <1>; 1214 interrupt-map-mask = <0 0 0 7>; 1215 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1216 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1217 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1218 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1219 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1220 status = "disabled"; 1221 }; 1222 1223 pcie3: pcie@3600000 { 1224 compatible = "fsl,lx2160a-pcie"; 1225 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 1226 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 1227 reg-names = "csr_axi_slave", "config_axi_slave"; 1228 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1229 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1230 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1231 interrupt-names = "aer", "pme", "intr"; 1232 #address-cells = <3>; 1233 #size-cells = <2>; 1234 device_type = "pci"; 1235 dma-coherent; 1236 apio-wins = <256>; 1237 ppio-wins = <24>; 1238 bus-range = <0x0 0xff>; 1239 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1240 msi-parent = <&its>; 1241 #interrupt-cells = <1>; 1242 interrupt-map-mask = <0 0 0 7>; 1243 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1244 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1245 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1246 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1247 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1248 status = "disabled"; 1249 }; 1250 1251 pcie4: pcie@3700000 { 1252 compatible = "fsl,lx2160a-pcie"; 1253 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ 1254 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 1255 reg-names = "csr_axi_slave", "config_axi_slave"; 1256 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1257 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1258 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1259 interrupt-names = "aer", "pme", "intr"; 1260 #address-cells = <3>; 1261 #size-cells = <2>; 1262 device_type = "pci"; 1263 dma-coherent; 1264 apio-wins = <8>; 1265 ppio-wins = <8>; 1266 bus-range = <0x0 0xff>; 1267 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1268 msi-parent = <&its>; 1269 #interrupt-cells = <1>; 1270 interrupt-map-mask = <0 0 0 7>; 1271 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1272 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1273 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1274 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1275 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1276 status = "disabled"; 1277 }; 1278 1279 pcie5: pcie@3800000 { 1280 compatible = "fsl,lx2160a-pcie"; 1281 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ 1282 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 1283 reg-names = "csr_axi_slave", "config_axi_slave"; 1284 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1285 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1286 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1287 interrupt-names = "aer", "pme", "intr"; 1288 #address-cells = <3>; 1289 #size-cells = <2>; 1290 device_type = "pci"; 1291 dma-coherent; 1292 apio-wins = <256>; 1293 ppio-wins = <24>; 1294 bus-range = <0x0 0xff>; 1295 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1296 msi-parent = <&its>; 1297 #interrupt-cells = <1>; 1298 interrupt-map-mask = <0 0 0 7>; 1299 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1300 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1301 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1302 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1303 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1304 status = "disabled"; 1305 }; 1306 1307 pcie6: pcie@3900000 { 1308 compatible = "fsl,lx2160a-pcie"; 1309 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ 1310 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 1311 reg-names = "csr_axi_slave", "config_axi_slave"; 1312 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1313 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1314 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1315 interrupt-names = "aer", "pme", "intr"; 1316 #address-cells = <3>; 1317 #size-cells = <2>; 1318 device_type = "pci"; 1319 dma-coherent; 1320 apio-wins = <8>; 1321 ppio-wins = <8>; 1322 bus-range = <0x0 0xff>; 1323 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1324 msi-parent = <&its>; 1325 #interrupt-cells = <1>; 1326 interrupt-map-mask = <0 0 0 7>; 1327 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1328 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1329 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1330 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1331 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1332 status = "disabled"; 1333 }; 1334 1335 smmu: iommu@5000000 { 1336 compatible = "arm,mmu-500"; 1337 reg = <0 0x5000000 0 0x800000>; 1338 #iommu-cells = <1>; 1339 #global-interrupts = <14>; 1340 // global secure fault 1341 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1342 // combined secure 1343 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1344 // global non-secure fault 1345 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1346 // combined non-secure 1347 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1348 // performance counter interrupts 0-9 1349 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1359 // per context interrupt, 64 interrupts 1360 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1424 dma-coherent; 1425 }; 1426 1427 console@8340020 { 1428 compatible = "fsl,dpaa2-console"; 1429 reg = <0x00000000 0x08340020 0 0x2>; 1430 }; 1431 1432 ptp-timer@8b95000 { 1433 compatible = "fsl,dpaa2-ptp"; 1434 reg = <0x0 0x8b95000 0x0 0x100>; 1435 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1436 QORIQ_CLK_PLL_DIV(2)>; 1437 little-endian; 1438 fsl,extts-fifo; 1439 }; 1440 1441 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 1442 emdio1: mdio@8b96000 { 1443 compatible = "fsl,fman-memac-mdio"; 1444 reg = <0x0 0x8b96000 0x0 0x1000>; 1445 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 little-endian; 1449 clock-frequency = <2500000>; 1450 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1451 QORIQ_CLK_PLL_DIV(2)>; 1452 status = "disabled"; 1453 }; 1454 1455 emdio2: mdio@8b97000 { 1456 compatible = "fsl,fman-memac-mdio"; 1457 reg = <0x0 0x8b97000 0x0 0x1000>; 1458 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1459 little-endian; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 clock-frequency = <2500000>; 1463 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1464 QORIQ_CLK_PLL_DIV(2)>; 1465 status = "disabled"; 1466 }; 1467 1468 pcs_mdio1: mdio@8c07000 { 1469 compatible = "fsl,fman-memac-mdio"; 1470 reg = <0x0 0x8c07000 0x0 0x1000>; 1471 little-endian; 1472 #address-cells = <1>; 1473 #size-cells = <0>; 1474 status = "disabled"; 1475 1476 pcs1: ethernet-phy@0 { 1477 reg = <0>; 1478 }; 1479 }; 1480 1481 pcs_mdio2: mdio@8c0b000 { 1482 compatible = "fsl,fman-memac-mdio"; 1483 reg = <0x0 0x8c0b000 0x0 0x1000>; 1484 little-endian; 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 status = "disabled"; 1488 1489 pcs2: ethernet-phy@0 { 1490 reg = <0>; 1491 }; 1492 }; 1493 1494 pcs_mdio3: mdio@8c0f000 { 1495 compatible = "fsl,fman-memac-mdio"; 1496 reg = <0x0 0x8c0f000 0x0 0x1000>; 1497 little-endian; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 status = "disabled"; 1501 1502 pcs3: ethernet-phy@0 { 1503 reg = <0>; 1504 }; 1505 }; 1506 1507 pcs_mdio4: mdio@8c13000 { 1508 compatible = "fsl,fman-memac-mdio"; 1509 reg = <0x0 0x8c13000 0x0 0x1000>; 1510 little-endian; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 1515 pcs4: ethernet-phy@0 { 1516 reg = <0>; 1517 }; 1518 }; 1519 1520 pcs_mdio5: mdio@8c17000 { 1521 compatible = "fsl,fman-memac-mdio"; 1522 reg = <0x0 0x8c17000 0x0 0x1000>; 1523 little-endian; 1524 #address-cells = <1>; 1525 #size-cells = <0>; 1526 status = "disabled"; 1527 1528 pcs5: ethernet-phy@0 { 1529 reg = <0>; 1530 }; 1531 }; 1532 1533 pcs_mdio6: mdio@8c1b000 { 1534 compatible = "fsl,fman-memac-mdio"; 1535 reg = <0x0 0x8c1b000 0x0 0x1000>; 1536 little-endian; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 status = "disabled"; 1540 1541 pcs6: ethernet-phy@0 { 1542 reg = <0>; 1543 }; 1544 }; 1545 1546 pcs_mdio7: mdio@8c1f000 { 1547 compatible = "fsl,fman-memac-mdio"; 1548 reg = <0x0 0x8c1f000 0x0 0x1000>; 1549 little-endian; 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 status = "disabled"; 1553 1554 pcs7: ethernet-phy@0 { 1555 reg = <0>; 1556 }; 1557 }; 1558 1559 pcs_mdio8: mdio@8c23000 { 1560 compatible = "fsl,fman-memac-mdio"; 1561 reg = <0x0 0x8c23000 0x0 0x1000>; 1562 little-endian; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 status = "disabled"; 1566 1567 pcs8: ethernet-phy@0 { 1568 reg = <0>; 1569 }; 1570 }; 1571 1572 pcs_mdio9: mdio@8c27000 { 1573 compatible = "fsl,fman-memac-mdio"; 1574 reg = <0x0 0x8c27000 0x0 0x1000>; 1575 little-endian; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 status = "disabled"; 1579 1580 pcs9: ethernet-phy@0 { 1581 reg = <0>; 1582 }; 1583 }; 1584 1585 pcs_mdio10: mdio@8c2b000 { 1586 compatible = "fsl,fman-memac-mdio"; 1587 reg = <0x0 0x8c2b000 0x0 0x1000>; 1588 little-endian; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 status = "disabled"; 1592 1593 pcs10: ethernet-phy@0 { 1594 reg = <0>; 1595 }; 1596 }; 1597 1598 pcs_mdio11: mdio@8c2f000 { 1599 compatible = "fsl,fman-memac-mdio"; 1600 reg = <0x0 0x8c2f000 0x0 0x1000>; 1601 little-endian; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 status = "disabled"; 1605 1606 pcs11: ethernet-phy@0 { 1607 reg = <0>; 1608 }; 1609 }; 1610 1611 pcs_mdio12: mdio@8c33000 { 1612 compatible = "fsl,fman-memac-mdio"; 1613 reg = <0x0 0x8c33000 0x0 0x1000>; 1614 little-endian; 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 status = "disabled"; 1618 1619 pcs12: ethernet-phy@0 { 1620 reg = <0>; 1621 }; 1622 }; 1623 1624 pcs_mdio13: mdio@8c37000 { 1625 compatible = "fsl,fman-memac-mdio"; 1626 reg = <0x0 0x8c37000 0x0 0x1000>; 1627 little-endian; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 status = "disabled"; 1631 1632 pcs13: ethernet-phy@0 { 1633 reg = <0>; 1634 }; 1635 }; 1636 1637 pcs_mdio14: mdio@8c3b000 { 1638 compatible = "fsl,fman-memac-mdio"; 1639 reg = <0x0 0x8c3b000 0x0 0x1000>; 1640 little-endian; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 status = "disabled"; 1644 1645 pcs14: ethernet-phy@0 { 1646 reg = <0>; 1647 }; 1648 }; 1649 1650 pcs_mdio15: mdio@8c3f000 { 1651 compatible = "fsl,fman-memac-mdio"; 1652 reg = <0x0 0x8c3f000 0x0 0x1000>; 1653 little-endian; 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 status = "disabled"; 1657 1658 pcs15: ethernet-phy@0 { 1659 reg = <0>; 1660 }; 1661 }; 1662 1663 pcs_mdio16: mdio@8c43000 { 1664 compatible = "fsl,fman-memac-mdio"; 1665 reg = <0x0 0x8c43000 0x0 0x1000>; 1666 little-endian; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 1671 pcs16: ethernet-phy@0 { 1672 reg = <0>; 1673 }; 1674 }; 1675 1676 pcs_mdio17: mdio@8c47000 { 1677 compatible = "fsl,fman-memac-mdio"; 1678 reg = <0x0 0x8c47000 0x0 0x1000>; 1679 little-endian; 1680 #address-cells = <1>; 1681 #size-cells = <0>; 1682 status = "disabled"; 1683 1684 pcs17: ethernet-phy@0 { 1685 reg = <0>; 1686 }; 1687 }; 1688 1689 pcs_mdio18: mdio@8c4b000 { 1690 compatible = "fsl,fman-memac-mdio"; 1691 reg = <0x0 0x8c4b000 0x0 0x1000>; 1692 little-endian; 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 status = "disabled"; 1696 1697 pcs18: ethernet-phy@0 { 1698 reg = <0>; 1699 }; 1700 }; 1701 1702 pinmux_i2crv: pinmux@70010012c { 1703 compatible = "pinctrl-single"; 1704 reg = <0x00000007 0x0010012c 0x0 0xc>; 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 pinctrl-single,bit-per-mux; 1708 pinctrl-single,register-width = <32>; 1709 pinctrl-single,function-mask = <0x7>; 1710 1711 i2c1_scl: i2c1-scl-pins { 1712 pinctrl-single,bits = <0x0 0 0x7>; 1713 }; 1714 1715 i2c1_scl_gpio: i2c1-scl-gpio-pins { 1716 pinctrl-single,bits = <0x0 0x1 0x7>; 1717 }; 1718 1719 i2c2_scl: i2c2-scl-pins { 1720 pinctrl-single,bits = <0x0 0 (0x7 << 3)>; 1721 }; 1722 1723 i2c2_scl_gpio: i2c2-scl-gpio-pins { 1724 pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>; 1725 }; 1726 1727 i2c3_scl: i2c3-scl-pins { 1728 pinctrl-single,bits = <0x0 0 (0x7 << 6)>; 1729 }; 1730 1731 i2c3_scl_gpio: i2c3-scl-gpio-pins { 1732 pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>; 1733 }; 1734 1735 i2c4_scl: i2c4-scl-pins { 1736 pinctrl-single,bits = <0x0 0 (0x7 << 9)>; 1737 }; 1738 1739 i2c4_scl_gpio: i2c4-scl-gpio-pins { 1740 pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>; 1741 }; 1742 1743 i2c5_scl: i2c5-scl-pins { 1744 pinctrl-single,bits = <0x0 0 (0x7 << 12)>; 1745 }; 1746 1747 i2c5_scl_gpio: i2c5-scl-gpio-pins { 1748 pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>; 1749 }; 1750 1751 i2c6_scl: i2c6-scl-pins { 1752 pinctrl-single,bits = <0x4 0x2 0x7>; 1753 }; 1754 1755 i2c6_scl_gpio: i2c6-scl-gpio-pins { 1756 pinctrl-single,bits = <0x4 0x1 0x7>; 1757 }; 1758 1759 i2c7_scl: i2c7-scl-pins { 1760 pinctrl-single,bits = <0x4 0x2 0x7>; 1761 }; 1762 1763 i2c7_scl_gpio: i2c7-scl-gpio-pins { 1764 pinctrl-single,bits = <0x4 0x1 0x7>; 1765 }; 1766 1767 i2c0_scl: i2c0-scl-pins { 1768 pinctrl-single,bits = <0x8 0 (0x7 << 10)>; 1769 }; 1770 1771 i2c0_scl_gpio: i2c0-scl-gpio-pins { 1772 pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>; 1773 }; 1774 }; 1775 1776 fsl_mc: fsl-mc@80c000000 { 1777 compatible = "fsl,qoriq-mc"; 1778 reg = <0x00000008 0x0c000000 0 0x40>, 1779 <0x00000000 0x08340000 0 0x40000>; 1780 msi-parent = <&its>; 1781 /* iommu-map property is fixed up by u-boot */ 1782 iommu-map = <0 &smmu 0 0>; 1783 dma-coherent; 1784 #address-cells = <3>; 1785 #size-cells = <1>; 1786 1787 /* 1788 * Region type 0x0 - MC portals 1789 * Region type 0x1 - QBMAN portals 1790 */ 1791 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1792 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1793 1794 /* 1795 * Define the maximum number of MACs present on the SoC. 1796 */ 1797 dpmacs { 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 1801 dpmac1: ethernet@1 { 1802 compatible = "fsl,qoriq-mc-dpmac"; 1803 reg = <0x1>; 1804 pcs-handle = <&pcs1>; 1805 }; 1806 1807 dpmac2: ethernet@2 { 1808 compatible = "fsl,qoriq-mc-dpmac"; 1809 reg = <0x2>; 1810 pcs-handle = <&pcs2>; 1811 }; 1812 1813 dpmac3: ethernet@3 { 1814 compatible = "fsl,qoriq-mc-dpmac"; 1815 reg = <0x3>; 1816 pcs-handle = <&pcs3>; 1817 }; 1818 1819 dpmac4: ethernet@4 { 1820 compatible = "fsl,qoriq-mc-dpmac"; 1821 reg = <0x4>; 1822 pcs-handle = <&pcs4>; 1823 }; 1824 1825 dpmac5: ethernet@5 { 1826 compatible = "fsl,qoriq-mc-dpmac"; 1827 reg = <0x5>; 1828 pcs-handle = <&pcs5>; 1829 }; 1830 1831 dpmac6: ethernet@6 { 1832 compatible = "fsl,qoriq-mc-dpmac"; 1833 reg = <0x6>; 1834 pcs-handle = <&pcs6>; 1835 }; 1836 1837 dpmac7: ethernet@7 { 1838 compatible = "fsl,qoriq-mc-dpmac"; 1839 reg = <0x7>; 1840 pcs-handle = <&pcs7>; 1841 }; 1842 1843 dpmac8: ethernet@8 { 1844 compatible = "fsl,qoriq-mc-dpmac"; 1845 reg = <0x8>; 1846 pcs-handle = <&pcs8>; 1847 }; 1848 1849 dpmac9: ethernet@9 { 1850 compatible = "fsl,qoriq-mc-dpmac"; 1851 reg = <0x9>; 1852 pcs-handle = <&pcs9>; 1853 }; 1854 1855 dpmac10: ethernet@a { 1856 compatible = "fsl,qoriq-mc-dpmac"; 1857 reg = <0xa>; 1858 pcs-handle = <&pcs10>; 1859 }; 1860 1861 dpmac11: ethernet@b { 1862 compatible = "fsl,qoriq-mc-dpmac"; 1863 reg = <0xb>; 1864 pcs-handle = <&pcs11>; 1865 }; 1866 1867 dpmac12: ethernet@c { 1868 compatible = "fsl,qoriq-mc-dpmac"; 1869 reg = <0xc>; 1870 pcs-handle = <&pcs12>; 1871 }; 1872 1873 dpmac13: ethernet@d { 1874 compatible = "fsl,qoriq-mc-dpmac"; 1875 reg = <0xd>; 1876 pcs-handle = <&pcs13>; 1877 }; 1878 1879 dpmac14: ethernet@e { 1880 compatible = "fsl,qoriq-mc-dpmac"; 1881 reg = <0xe>; 1882 pcs-handle = <&pcs14>; 1883 }; 1884 1885 dpmac15: ethernet@f { 1886 compatible = "fsl,qoriq-mc-dpmac"; 1887 reg = <0xf>; 1888 pcs-handle = <&pcs15>; 1889 }; 1890 1891 dpmac16: ethernet@10 { 1892 compatible = "fsl,qoriq-mc-dpmac"; 1893 reg = <0x10>; 1894 pcs-handle = <&pcs16>; 1895 }; 1896 1897 dpmac17: ethernet@11 { 1898 compatible = "fsl,qoriq-mc-dpmac"; 1899 reg = <0x11>; 1900 pcs-handle = <&pcs17>; 1901 }; 1902 1903 dpmac18: ethernet@12 { 1904 compatible = "fsl,qoriq-mc-dpmac"; 1905 reg = <0x12>; 1906 pcs-handle = <&pcs18>; 1907 }; 1908 }; 1909 }; 1910 }; 1911 1912 firmware { 1913 optee: optee { 1914 compatible = "linaro,optee-tz"; 1915 method = "smc"; 1916 status = "disabled"; 1917 }; 1918 }; 1919}; 1920