1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/memreserve/ 0x80000000 0x00010000; 13 14/ { 15 compatible = "fsl,lx2160a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 rtc1 = &ftm_alarm0; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 // 8 clusters having 2 Cortex-A72 cores each 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a72"; 32 enable-method = "psci"; 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 d-cache-size = <0x8000>; 36 d-cache-line-size = <64>; 37 d-cache-sets = <128>; 38 i-cache-size = <0xC000>; 39 i-cache-line-size = <64>; 40 i-cache-sets = <192>; 41 next-level-cache = <&cluster0_l2>; 42 cpu-idle-states = <&cpu_pw15>; 43 #cooling-cells = <2>; 44 }; 45 46 cpu1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a72"; 49 enable-method = "psci"; 50 reg = <0x1>; 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 52 d-cache-size = <0x8000>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 i-cache-size = <0xC000>; 56 i-cache-line-size = <64>; 57 i-cache-sets = <192>; 58 next-level-cache = <&cluster0_l2>; 59 cpu-idle-states = <&cpu_pw15>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu100: cpu@100 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a72"; 66 enable-method = "psci"; 67 reg = <0x100>; 68 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 69 d-cache-size = <0x8000>; 70 d-cache-line-size = <64>; 71 d-cache-sets = <128>; 72 i-cache-size = <0xC000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <192>; 75 next-level-cache = <&cluster1_l2>; 76 cpu-idle-states = <&cpu_pw15>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu101: cpu@101 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a72"; 83 enable-method = "psci"; 84 reg = <0x101>; 85 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 86 d-cache-size = <0x8000>; 87 d-cache-line-size = <64>; 88 d-cache-sets = <128>; 89 i-cache-size = <0xC000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <192>; 92 next-level-cache = <&cluster1_l2>; 93 cpu-idle-states = <&cpu_pw15>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu200: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a72"; 100 enable-method = "psci"; 101 reg = <0x200>; 102 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 103 d-cache-size = <0x8000>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 i-cache-size = <0xC000>; 107 i-cache-line-size = <64>; 108 i-cache-sets = <192>; 109 next-level-cache = <&cluster2_l2>; 110 cpu-idle-states = <&cpu_pw15>; 111 #cooling-cells = <2>; 112 }; 113 114 cpu201: cpu@201 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a72"; 117 enable-method = "psci"; 118 reg = <0x201>; 119 clocks = <&clockgen QORIQ_CLK_CMUX 2>; 120 d-cache-size = <0x8000>; 121 d-cache-line-size = <64>; 122 d-cache-sets = <128>; 123 i-cache-size = <0xC000>; 124 i-cache-line-size = <64>; 125 i-cache-sets = <192>; 126 next-level-cache = <&cluster2_l2>; 127 cpu-idle-states = <&cpu_pw15>; 128 #cooling-cells = <2>; 129 }; 130 131 cpu300: cpu@300 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a72"; 134 enable-method = "psci"; 135 reg = <0x300>; 136 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 137 d-cache-size = <0x8000>; 138 d-cache-line-size = <64>; 139 d-cache-sets = <128>; 140 i-cache-size = <0xC000>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <192>; 143 next-level-cache = <&cluster3_l2>; 144 cpu-idle-states = <&cpu_pw15>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu301: cpu@301 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a72"; 151 enable-method = "psci"; 152 reg = <0x301>; 153 clocks = <&clockgen QORIQ_CLK_CMUX 3>; 154 d-cache-size = <0x8000>; 155 d-cache-line-size = <64>; 156 d-cache-sets = <128>; 157 i-cache-size = <0xC000>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <192>; 160 next-level-cache = <&cluster3_l2>; 161 cpu-idle-states = <&cpu_pw15>; 162 #cooling-cells = <2>; 163 }; 164 165 cpu400: cpu@400 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a72"; 168 enable-method = "psci"; 169 reg = <0x400>; 170 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 171 d-cache-size = <0x8000>; 172 d-cache-line-size = <64>; 173 d-cache-sets = <128>; 174 i-cache-size = <0xC000>; 175 i-cache-line-size = <64>; 176 i-cache-sets = <192>; 177 next-level-cache = <&cluster4_l2>; 178 cpu-idle-states = <&cpu_pw15>; 179 #cooling-cells = <2>; 180 }; 181 182 cpu401: cpu@401 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a72"; 185 enable-method = "psci"; 186 reg = <0x401>; 187 clocks = <&clockgen QORIQ_CLK_CMUX 4>; 188 d-cache-size = <0x8000>; 189 d-cache-line-size = <64>; 190 d-cache-sets = <128>; 191 i-cache-size = <0xC000>; 192 i-cache-line-size = <64>; 193 i-cache-sets = <192>; 194 next-level-cache = <&cluster4_l2>; 195 cpu-idle-states = <&cpu_pw15>; 196 #cooling-cells = <2>; 197 }; 198 199 cpu500: cpu@500 { 200 device_type = "cpu"; 201 compatible = "arm,cortex-a72"; 202 enable-method = "psci"; 203 reg = <0x500>; 204 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 205 d-cache-size = <0x8000>; 206 d-cache-line-size = <64>; 207 d-cache-sets = <128>; 208 i-cache-size = <0xC000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <192>; 211 next-level-cache = <&cluster5_l2>; 212 cpu-idle-states = <&cpu_pw15>; 213 #cooling-cells = <2>; 214 }; 215 216 cpu501: cpu@501 { 217 device_type = "cpu"; 218 compatible = "arm,cortex-a72"; 219 enable-method = "psci"; 220 reg = <0x501>; 221 clocks = <&clockgen QORIQ_CLK_CMUX 5>; 222 d-cache-size = <0x8000>; 223 d-cache-line-size = <64>; 224 d-cache-sets = <128>; 225 i-cache-size = <0xC000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <192>; 228 next-level-cache = <&cluster5_l2>; 229 cpu-idle-states = <&cpu_pw15>; 230 #cooling-cells = <2>; 231 }; 232 233 cpu600: cpu@600 { 234 device_type = "cpu"; 235 compatible = "arm,cortex-a72"; 236 enable-method = "psci"; 237 reg = <0x600>; 238 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 239 d-cache-size = <0x8000>; 240 d-cache-line-size = <64>; 241 d-cache-sets = <128>; 242 i-cache-size = <0xC000>; 243 i-cache-line-size = <64>; 244 i-cache-sets = <192>; 245 next-level-cache = <&cluster6_l2>; 246 cpu-idle-states = <&cpu_pw15>; 247 #cooling-cells = <2>; 248 }; 249 250 cpu601: cpu@601 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 enable-method = "psci"; 254 reg = <0x601>; 255 clocks = <&clockgen QORIQ_CLK_CMUX 6>; 256 d-cache-size = <0x8000>; 257 d-cache-line-size = <64>; 258 d-cache-sets = <128>; 259 i-cache-size = <0xC000>; 260 i-cache-line-size = <64>; 261 i-cache-sets = <192>; 262 next-level-cache = <&cluster6_l2>; 263 cpu-idle-states = <&cpu_pw15>; 264 #cooling-cells = <2>; 265 }; 266 267 cpu700: cpu@700 { 268 device_type = "cpu"; 269 compatible = "arm,cortex-a72"; 270 enable-method = "psci"; 271 reg = <0x700>; 272 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 273 d-cache-size = <0x8000>; 274 d-cache-line-size = <64>; 275 d-cache-sets = <128>; 276 i-cache-size = <0xC000>; 277 i-cache-line-size = <64>; 278 i-cache-sets = <192>; 279 next-level-cache = <&cluster7_l2>; 280 cpu-idle-states = <&cpu_pw15>; 281 #cooling-cells = <2>; 282 }; 283 284 cpu701: cpu@701 { 285 device_type = "cpu"; 286 compatible = "arm,cortex-a72"; 287 enable-method = "psci"; 288 reg = <0x701>; 289 clocks = <&clockgen QORIQ_CLK_CMUX 7>; 290 d-cache-size = <0x8000>; 291 d-cache-line-size = <64>; 292 d-cache-sets = <128>; 293 i-cache-size = <0xC000>; 294 i-cache-line-size = <64>; 295 i-cache-sets = <192>; 296 next-level-cache = <&cluster7_l2>; 297 cpu-idle-states = <&cpu_pw15>; 298 #cooling-cells = <2>; 299 }; 300 301 cluster0_l2: l2-cache0 { 302 compatible = "cache"; 303 cache-unified; 304 cache-size = <0x100000>; 305 cache-line-size = <64>; 306 cache-sets = <1024>; 307 cache-level = <2>; 308 }; 309 310 cluster1_l2: l2-cache1 { 311 compatible = "cache"; 312 cache-unified; 313 cache-size = <0x100000>; 314 cache-line-size = <64>; 315 cache-sets = <1024>; 316 cache-level = <2>; 317 }; 318 319 cluster2_l2: l2-cache2 { 320 compatible = "cache"; 321 cache-unified; 322 cache-size = <0x100000>; 323 cache-line-size = <64>; 324 cache-sets = <1024>; 325 cache-level = <2>; 326 }; 327 328 cluster3_l2: l2-cache3 { 329 compatible = "cache"; 330 cache-unified; 331 cache-size = <0x100000>; 332 cache-line-size = <64>; 333 cache-sets = <1024>; 334 cache-level = <2>; 335 }; 336 337 cluster4_l2: l2-cache4 { 338 compatible = "cache"; 339 cache-unified; 340 cache-size = <0x100000>; 341 cache-line-size = <64>; 342 cache-sets = <1024>; 343 cache-level = <2>; 344 }; 345 346 cluster5_l2: l2-cache5 { 347 compatible = "cache"; 348 cache-unified; 349 cache-size = <0x100000>; 350 cache-line-size = <64>; 351 cache-sets = <1024>; 352 cache-level = <2>; 353 }; 354 355 cluster6_l2: l2-cache6 { 356 compatible = "cache"; 357 cache-unified; 358 cache-size = <0x100000>; 359 cache-line-size = <64>; 360 cache-sets = <1024>; 361 cache-level = <2>; 362 }; 363 364 cluster7_l2: l2-cache7 { 365 compatible = "cache"; 366 cache-unified; 367 cache-size = <0x100000>; 368 cache-line-size = <64>; 369 cache-sets = <1024>; 370 cache-level = <2>; 371 }; 372 373 cpu_pw15: cpu-pw15 { 374 compatible = "arm,idle-state"; 375 idle-state-name = "PW15"; 376 arm,psci-suspend-param = <0x0>; 377 entry-latency-us = <2000>; 378 exit-latency-us = <2000>; 379 min-residency-us = <6000>; 380 }; 381 }; 382 383 gic: interrupt-controller@6000000 { 384 compatible = "arm,gic-v3"; 385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 387 // SGI_base) 388 <0x0 0x0c0c0000 0 0x2000>, // GICC 389 <0x0 0x0c0d0000 0 0x1000>, // GICH 390 <0x0 0x0c0e0000 0 0x20000>; // GICV 391 #interrupt-cells = <3>; 392 #address-cells = <2>; 393 #size-cells = <2>; 394 ranges; 395 interrupt-controller; 396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 397 398 its: gic-its@6020000 { 399 compatible = "arm,gic-v3-its"; 400 msi-controller; 401 reg = <0x0 0x6020000 0 0x20000>; 402 }; 403 }; 404 405 timer { 406 compatible = "arm,armv8-timer"; 407 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 411 }; 412 413 pmu { 414 compatible = "arm,cortex-a72-pmu"; 415 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 416 }; 417 418 psci { 419 compatible = "arm,psci-0.2"; 420 method = "smc"; 421 }; 422 423 memory@80000000 { 424 // DRAM space - 1, size : 2 GB DRAM 425 device_type = "memory"; 426 reg = <0x00000000 0x80000000 0 0x80000000>; 427 }; 428 429 ddr1: memory-controller@1080000 { 430 compatible = "fsl,qoriq-memory-controller"; 431 reg = <0x0 0x1080000 0x0 0x1000>; 432 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 433 little-endian; 434 }; 435 436 ddr2: memory-controller@1090000 { 437 compatible = "fsl,qoriq-memory-controller"; 438 reg = <0x0 0x1090000 0x0 0x1000>; 439 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 440 little-endian; 441 }; 442 443 // One clock unit-sysclk node which bootloader require during DT fix-up 444 sysclk: sysclk { 445 compatible = "fixed-clock"; 446 #clock-cells = <0>; 447 clock-frequency = <100000000>; // fixed up by bootloader 448 clock-output-names = "sysclk"; 449 }; 450 451 thermal-zones { 452 cluster6-7 { 453 polling-delay-passive = <1000>; 454 polling-delay = <5000>; 455 thermal-sensors = <&tmu 0>; 456 457 trips { 458 cluster6_7_alert: cluster6-7-alert { 459 temperature = <85000>; 460 hysteresis = <2000>; 461 type = "passive"; 462 }; 463 464 cluster6_7_crit: cluster6-7-crit { 465 temperature = <95000>; 466 hysteresis = <2000>; 467 type = "critical"; 468 }; 469 }; 470 471 cooling-maps { 472 map0 { 473 trip = <&cluster6_7_alert>; 474 cooling-device = 475 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 476 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 477 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 478 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 479 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 480 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 481 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 482 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 483 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 484 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 485 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 486 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 487 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 488 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 489 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 490 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 491 }; 492 }; 493 }; 494 495 ddr-cluster5 { 496 polling-delay-passive = <1000>; 497 polling-delay = <5000>; 498 thermal-sensors = <&tmu 1>; 499 500 trips { 501 ddr-cluster5-alert { 502 temperature = <85000>; 503 hysteresis = <2000>; 504 type = "passive"; 505 }; 506 507 ddr-cluster5-crit { 508 temperature = <95000>; 509 hysteresis = <2000>; 510 type = "critical"; 511 }; 512 }; 513 }; 514 515 wriop { 516 polling-delay-passive = <1000>; 517 polling-delay = <5000>; 518 thermal-sensors = <&tmu 2>; 519 520 trips { 521 wriop-alert { 522 temperature = <85000>; 523 hysteresis = <2000>; 524 type = "passive"; 525 }; 526 527 wriop-crit { 528 temperature = <95000>; 529 hysteresis = <2000>; 530 type = "critical"; 531 }; 532 }; 533 }; 534 535 dce-qbman-hsio2 { 536 polling-delay-passive = <1000>; 537 polling-delay = <5000>; 538 thermal-sensors = <&tmu 3>; 539 540 trips { 541 dce-qbman-alert { 542 temperature = <85000>; 543 hysteresis = <2000>; 544 type = "passive"; 545 }; 546 547 dce-qbman-crit { 548 temperature = <95000>; 549 hysteresis = <2000>; 550 type = "critical"; 551 }; 552 }; 553 }; 554 555 ccn-dpaa-tbu { 556 polling-delay-passive = <1000>; 557 polling-delay = <5000>; 558 thermal-sensors = <&tmu 4>; 559 560 trips { 561 ccn-dpaa-alert { 562 temperature = <85000>; 563 hysteresis = <2000>; 564 type = "passive"; 565 }; 566 567 ccn-dpaa-crit { 568 temperature = <95000>; 569 hysteresis = <2000>; 570 type = "critical"; 571 }; 572 }; 573 }; 574 575 cluster4-hsio3 { 576 polling-delay-passive = <1000>; 577 polling-delay = <5000>; 578 thermal-sensors = <&tmu 5>; 579 580 trips { 581 clust4-hsio3-alert { 582 temperature = <85000>; 583 hysteresis = <2000>; 584 type = "passive"; 585 }; 586 587 clust4-hsio3-crit { 588 temperature = <95000>; 589 hysteresis = <2000>; 590 type = "critical"; 591 }; 592 }; 593 }; 594 595 cluster2-3 { 596 polling-delay-passive = <1000>; 597 polling-delay = <5000>; 598 thermal-sensors = <&tmu 6>; 599 600 trips { 601 cluster2-3-alert { 602 temperature = <85000>; 603 hysteresis = <2000>; 604 type = "passive"; 605 }; 606 607 cluster2-3-crit { 608 temperature = <95000>; 609 hysteresis = <2000>; 610 type = "critical"; 611 }; 612 }; 613 }; 614 }; 615 616 soc { 617 compatible = "simple-bus"; 618 #address-cells = <2>; 619 #size-cells = <2>; 620 ranges; 621 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 622 623 serdes_1: phy@1ea0000 { 624 compatible = "fsl,lynx-28g"; 625 reg = <0x0 0x1ea0000 0x0 0x1e30>; 626 #phy-cells = <1>; 627 }; 628 629 crypto: crypto@8000000 { 630 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 631 fsl,sec-era = <10>; 632 #address-cells = <1>; 633 #size-cells = <1>; 634 ranges = <0x0 0x00 0x8000000 0x100000>; 635 reg = <0x00 0x8000000 0x0 0x100000>; 636 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 637 dma-coherent; 638 status = "disabled"; 639 640 sec_jr0: jr@10000 { 641 compatible = "fsl,sec-v5.0-job-ring", 642 "fsl,sec-v4.0-job-ring"; 643 reg = <0x10000 0x10000>; 644 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 645 }; 646 647 sec_jr1: jr@20000 { 648 compatible = "fsl,sec-v5.0-job-ring", 649 "fsl,sec-v4.0-job-ring"; 650 reg = <0x20000 0x10000>; 651 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 652 }; 653 654 sec_jr2: jr@30000 { 655 compatible = "fsl,sec-v5.0-job-ring", 656 "fsl,sec-v4.0-job-ring"; 657 reg = <0x30000 0x10000>; 658 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 659 }; 660 661 sec_jr3: jr@40000 { 662 compatible = "fsl,sec-v5.0-job-ring", 663 "fsl,sec-v4.0-job-ring"; 664 reg = <0x40000 0x10000>; 665 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 666 }; 667 }; 668 669 clockgen: clock-controller@1300000 { 670 compatible = "fsl,lx2160a-clockgen"; 671 reg = <0 0x1300000 0 0xa0000>; 672 #clock-cells = <2>; 673 clocks = <&sysclk>; 674 }; 675 676 dcfg: syscon@1e00000 { 677 compatible = "fsl,lx2160a-dcfg", "syscon"; 678 reg = <0x0 0x1e00000 0x0 0x10000>; 679 little-endian; 680 }; 681 682 sfp: efuse@1e80000 { 683 compatible = "fsl,ls1028a-sfp"; 684 reg = <0x0 0x1e80000 0x0 0x10000>; 685 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 686 QORIQ_CLK_PLL_DIV(4)>; 687 clock-names = "sfp"; 688 }; 689 690 isc: syscon@1f70000 { 691 compatible = "fsl,lx2160a-isc", "syscon"; 692 reg = <0x0 0x1f70000 0x0 0x10000>; 693 little-endian; 694 #address-cells = <1>; 695 #size-cells = <1>; 696 ranges = <0x0 0x0 0x1f70000 0x10000>; 697 698 extirq: interrupt-controller@14 { 699 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq"; 700 #interrupt-cells = <2>; 701 #address-cells = <0>; 702 interrupt-controller; 703 reg = <0x14 4>; 704 interrupt-map = 705 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 706 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 707 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 708 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 709 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 710 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 711 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 712 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 713 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 714 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 715 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 716 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 717 interrupt-map-mask = <0xf 0x0>; 718 }; 719 }; 720 721 tmu: tmu@1f80000 { 722 compatible = "fsl,qoriq-tmu"; 723 reg = <0x0 0x1f80000 0x0 0x10000>; 724 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 725 fsl,tmu-range = <0x800000e6 0x8001017d>; 726 fsl,tmu-calibration = 727 /* Calibration data group 1 */ 728 <0x00000000 0x00000035 729 /* Calibration data group 2 */ 730 0x00000001 0x00000154>; 731 little-endian; 732 #thermal-sensor-cells = <1>; 733 }; 734 735 i2c0: i2c@2000000 { 736 compatible = "fsl,vf610-i2c"; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 reg = <0x0 0x2000000 0x0 0x10000>; 740 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 741 clock-names = "i2c"; 742 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 743 QORIQ_CLK_PLL_DIV(16)>; 744 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 745 status = "disabled"; 746 }; 747 748 i2c1: i2c@2010000 { 749 compatible = "fsl,vf610-i2c"; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 reg = <0x0 0x2010000 0x0 0x10000>; 753 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 754 clock-names = "i2c"; 755 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 756 QORIQ_CLK_PLL_DIV(16)>; 757 status = "disabled"; 758 }; 759 760 i2c2: i2c@2020000 { 761 compatible = "fsl,vf610-i2c"; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 reg = <0x0 0x2020000 0x0 0x10000>; 765 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 766 clock-names = "i2c"; 767 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 768 QORIQ_CLK_PLL_DIV(16)>; 769 status = "disabled"; 770 }; 771 772 i2c3: i2c@2030000 { 773 compatible = "fsl,vf610-i2c"; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 reg = <0x0 0x2030000 0x0 0x10000>; 777 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 778 clock-names = "i2c"; 779 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 780 QORIQ_CLK_PLL_DIV(16)>; 781 status = "disabled"; 782 }; 783 784 i2c4: i2c@2040000 { 785 compatible = "fsl,vf610-i2c"; 786 #address-cells = <1>; 787 #size-cells = <0>; 788 reg = <0x0 0x2040000 0x0 0x10000>; 789 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 790 clock-names = "i2c"; 791 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 792 QORIQ_CLK_PLL_DIV(16)>; 793 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 794 status = "disabled"; 795 }; 796 797 i2c5: i2c@2050000 { 798 compatible = "fsl,vf610-i2c"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 reg = <0x0 0x2050000 0x0 0x10000>; 802 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 803 clock-names = "i2c"; 804 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 805 QORIQ_CLK_PLL_DIV(16)>; 806 status = "disabled"; 807 }; 808 809 i2c6: i2c@2060000 { 810 compatible = "fsl,vf610-i2c"; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 reg = <0x0 0x2060000 0x0 0x10000>; 814 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 815 clock-names = "i2c"; 816 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 817 QORIQ_CLK_PLL_DIV(16)>; 818 status = "disabled"; 819 }; 820 821 i2c7: i2c@2070000 { 822 compatible = "fsl,vf610-i2c"; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 reg = <0x0 0x2070000 0x0 0x10000>; 826 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 827 clock-names = "i2c"; 828 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 829 QORIQ_CLK_PLL_DIV(16)>; 830 status = "disabled"; 831 }; 832 833 fspi: spi@20c0000 { 834 compatible = "nxp,lx2160a-fspi"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 reg = <0x0 0x20c0000 0x0 0x10000>, 838 <0x0 0x20000000 0x0 0x10000000>; 839 reg-names = "fspi_base", "fspi_mmap"; 840 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 842 QORIQ_CLK_PLL_DIV(4)>, 843 <&clockgen QORIQ_CLK_PLATFORM_PLL 844 QORIQ_CLK_PLL_DIV(4)>; 845 clock-names = "fspi_en", "fspi"; 846 status = "disabled"; 847 }; 848 849 dspi0: spi@2100000 { 850 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 reg = <0x0 0x2100000 0x0 0x10000>; 854 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 856 QORIQ_CLK_PLL_DIV(8)>; 857 clock-names = "dspi"; 858 spi-num-chipselects = <5>; 859 bus-num = <0>; 860 status = "disabled"; 861 }; 862 863 dspi1: spi@2110000 { 864 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 reg = <0x0 0x2110000 0x0 0x10000>; 868 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 870 QORIQ_CLK_PLL_DIV(8)>; 871 clock-names = "dspi"; 872 spi-num-chipselects = <5>; 873 bus-num = <1>; 874 status = "disabled"; 875 }; 876 877 dspi2: spi@2120000 { 878 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 879 #address-cells = <1>; 880 #size-cells = <0>; 881 reg = <0x0 0x2120000 0x0 0x10000>; 882 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 884 QORIQ_CLK_PLL_DIV(8)>; 885 clock-names = "dspi"; 886 spi-num-chipselects = <5>; 887 bus-num = <2>; 888 status = "disabled"; 889 }; 890 891 esdhc0: esdhc@2140000 { 892 compatible = "fsl,esdhc"; 893 reg = <0x0 0x2140000 0x0 0x10000>; 894 interrupts = <0 28 0x4>; /* Level high type */ 895 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 896 QORIQ_CLK_PLL_DIV(2)>; 897 dma-coherent; 898 voltage-ranges = <1800 1800 3300 3300>; 899 sdhci,auto-cmd12; 900 little-endian; 901 bus-width = <4>; 902 status = "disabled"; 903 }; 904 905 esdhc1: esdhc@2150000 { 906 compatible = "fsl,esdhc"; 907 reg = <0x0 0x2150000 0x0 0x10000>; 908 interrupts = <0 63 0x4>; /* Level high type */ 909 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 910 QORIQ_CLK_PLL_DIV(2)>; 911 dma-coherent; 912 voltage-ranges = <1800 1800 3300 3300>; 913 sdhci,auto-cmd12; 914 broken-cd; 915 little-endian; 916 bus-width = <4>; 917 status = "disabled"; 918 }; 919 920 can0: can@2180000 { 921 compatible = "fsl,lx2160ar1-flexcan"; 922 reg = <0x0 0x2180000 0x0 0x10000>; 923 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 925 QORIQ_CLK_PLL_DIV(8)>, 926 <&clockgen QORIQ_CLK_SYSCLK 0>; 927 clock-names = "ipg", "per"; 928 fsl,clk-source = /bits/ 8 <0>; 929 status = "disabled"; 930 }; 931 932 can1: can@2190000 { 933 compatible = "fsl,lx2160ar1-flexcan"; 934 reg = <0x0 0x2190000 0x0 0x10000>; 935 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 936 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 937 QORIQ_CLK_PLL_DIV(8)>, 938 <&clockgen QORIQ_CLK_SYSCLK 0>; 939 clock-names = "ipg", "per"; 940 fsl,clk-source = /bits/ 8 <0>; 941 status = "disabled"; 942 }; 943 944 uart0: serial@21c0000 { 945 compatible = "arm,sbsa-uart","arm,pl011"; 946 reg = <0x0 0x21c0000 0x0 0x1000>; 947 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 948 current-speed = <115200>; 949 status = "disabled"; 950 }; 951 952 uart1: serial@21d0000 { 953 compatible = "arm,sbsa-uart","arm,pl011"; 954 reg = <0x0 0x21d0000 0x0 0x1000>; 955 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 956 current-speed = <115200>; 957 status = "disabled"; 958 }; 959 960 uart2: serial@21e0000 { 961 compatible = "arm,sbsa-uart","arm,pl011"; 962 reg = <0x0 0x21e0000 0x0 0x1000>; 963 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 964 current-speed = <115200>; 965 status = "disabled"; 966 }; 967 968 uart3: serial@21f0000 { 969 compatible = "arm,sbsa-uart","arm,pl011"; 970 reg = <0x0 0x21f0000 0x0 0x1000>; 971 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 972 current-speed = <115200>; 973 status = "disabled"; 974 }; 975 976 gpio0: gpio@2300000 { 977 compatible = "fsl,qoriq-gpio"; 978 reg = <0x0 0x2300000 0x0 0x10000>; 979 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 980 gpio-controller; 981 little-endian; 982 #gpio-cells = <2>; 983 interrupt-controller; 984 #interrupt-cells = <2>; 985 }; 986 987 gpio1: gpio@2310000 { 988 compatible = "fsl,qoriq-gpio"; 989 reg = <0x0 0x2310000 0x0 0x10000>; 990 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 991 gpio-controller; 992 little-endian; 993 #gpio-cells = <2>; 994 interrupt-controller; 995 #interrupt-cells = <2>; 996 }; 997 998 gpio2: gpio@2320000 { 999 compatible = "fsl,qoriq-gpio"; 1000 reg = <0x0 0x2320000 0x0 0x10000>; 1001 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1002 gpio-controller; 1003 little-endian; 1004 #gpio-cells = <2>; 1005 interrupt-controller; 1006 #interrupt-cells = <2>; 1007 }; 1008 1009 gpio3: gpio@2330000 { 1010 compatible = "fsl,qoriq-gpio"; 1011 reg = <0x0 0x2330000 0x0 0x10000>; 1012 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1013 gpio-controller; 1014 little-endian; 1015 #gpio-cells = <2>; 1016 interrupt-controller; 1017 #interrupt-cells = <2>; 1018 }; 1019 1020 watchdog@23a0000 { 1021 compatible = "arm,sbsa-gwdt"; 1022 reg = <0x0 0x23a0000 0 0x1000>, 1023 <0x0 0x2390000 0 0x1000>; 1024 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1025 timeout-sec = <30>; 1026 }; 1027 1028 rcpm: power-controller@1e34040 { 1029 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1030 reg = <0x0 0x1e34040 0x0 0x1c>; 1031 #fsl,rcpm-wakeup-cells = <7>; 1032 little-endian; 1033 }; 1034 1035 ftm_alarm0: timer@2800000 { 1036 compatible = "fsl,lx2160a-ftm-alarm"; 1037 reg = <0x0 0x2800000 0x0 0x10000>; 1038 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 1039 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1040 }; 1041 1042 usb0: usb@3100000 { 1043 compatible = "snps,dwc3"; 1044 reg = <0x0 0x3100000 0x0 0x10000>; 1045 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1046 dr_mode = "host"; 1047 snps,quirk-frame-length-adjustment = <0x20>; 1048 usb3-lpm-capable; 1049 snps,dis_rxdet_inp3_quirk; 1050 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1051 status = "disabled"; 1052 }; 1053 1054 usb1: usb@3110000 { 1055 compatible = "snps,dwc3"; 1056 reg = <0x0 0x3110000 0x0 0x10000>; 1057 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1058 dr_mode = "host"; 1059 snps,quirk-frame-length-adjustment = <0x20>; 1060 usb3-lpm-capable; 1061 snps,dis_rxdet_inp3_quirk; 1062 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 1063 status = "disabled"; 1064 }; 1065 1066 sata0: sata@3200000 { 1067 compatible = "fsl,lx2160a-ahci"; 1068 reg = <0x0 0x3200000 0x0 0x10000>, 1069 <0x7 0x100520 0x0 0x4>; 1070 reg-names = "ahci", "sata-ecc"; 1071 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1073 QORIQ_CLK_PLL_DIV(4)>; 1074 dma-coherent; 1075 status = "disabled"; 1076 }; 1077 1078 sata1: sata@3210000 { 1079 compatible = "fsl,lx2160a-ahci"; 1080 reg = <0x0 0x3210000 0x0 0x10000>, 1081 <0x7 0x100520 0x0 0x4>; 1082 reg-names = "ahci", "sata-ecc"; 1083 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1085 QORIQ_CLK_PLL_DIV(4)>; 1086 dma-coherent; 1087 status = "disabled"; 1088 }; 1089 1090 sata2: sata@3220000 { 1091 compatible = "fsl,lx2160a-ahci"; 1092 reg = <0x0 0x3220000 0x0 0x10000>, 1093 <0x7 0x100520 0x0 0x4>; 1094 reg-names = "ahci", "sata-ecc"; 1095 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1097 QORIQ_CLK_PLL_DIV(4)>; 1098 dma-coherent; 1099 status = "disabled"; 1100 }; 1101 1102 sata3: sata@3230000 { 1103 compatible = "fsl,lx2160a-ahci"; 1104 reg = <0x0 0x3230000 0x0 0x10000>, 1105 <0x7 0x100520 0x0 0x4>; 1106 reg-names = "ahci", "sata-ecc"; 1107 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1109 QORIQ_CLK_PLL_DIV(4)>; 1110 dma-coherent; 1111 status = "disabled"; 1112 }; 1113 1114 pcie1: pcie@3400000 { 1115 compatible = "fsl,lx2160a-pcie"; 1116 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 1117 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ 1118 reg-names = "csr_axi_slave", "config_axi_slave"; 1119 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1120 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1121 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1122 interrupt-names = "aer", "pme", "intr"; 1123 #address-cells = <3>; 1124 #size-cells = <2>; 1125 device_type = "pci"; 1126 dma-coherent; 1127 apio-wins = <8>; 1128 ppio-wins = <8>; 1129 bus-range = <0x0 0xff>; 1130 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1131 msi-parent = <&its>; 1132 #interrupt-cells = <1>; 1133 interrupt-map-mask = <0 0 0 7>; 1134 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1135 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1136 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1137 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1138 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1139 status = "disabled"; 1140 }; 1141 1142 pcie2: pcie@3500000 { 1143 compatible = "fsl,lx2160a-pcie"; 1144 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 1145 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ 1146 reg-names = "csr_axi_slave", "config_axi_slave"; 1147 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1148 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1149 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1150 interrupt-names = "aer", "pme", "intr"; 1151 #address-cells = <3>; 1152 #size-cells = <2>; 1153 device_type = "pci"; 1154 dma-coherent; 1155 apio-wins = <8>; 1156 ppio-wins = <8>; 1157 bus-range = <0x0 0xff>; 1158 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1159 msi-parent = <&its>; 1160 #interrupt-cells = <1>; 1161 interrupt-map-mask = <0 0 0 7>; 1162 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1163 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1164 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1165 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1166 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1167 status = "disabled"; 1168 }; 1169 1170 pcie3: pcie@3600000 { 1171 compatible = "fsl,lx2160a-pcie"; 1172 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 1173 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */ 1174 reg-names = "csr_axi_slave", "config_axi_slave"; 1175 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1176 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1177 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1178 interrupt-names = "aer", "pme", "intr"; 1179 #address-cells = <3>; 1180 #size-cells = <2>; 1181 device_type = "pci"; 1182 dma-coherent; 1183 apio-wins = <256>; 1184 ppio-wins = <24>; 1185 bus-range = <0x0 0xff>; 1186 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1187 msi-parent = <&its>; 1188 #interrupt-cells = <1>; 1189 interrupt-map-mask = <0 0 0 7>; 1190 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1191 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1192 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1193 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1194 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1195 status = "disabled"; 1196 }; 1197 1198 pcie4: pcie@3700000 { 1199 compatible = "fsl,lx2160a-pcie"; 1200 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */ 1201 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */ 1202 reg-names = "csr_axi_slave", "config_axi_slave"; 1203 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1204 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1205 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1206 interrupt-names = "aer", "pme", "intr"; 1207 #address-cells = <3>; 1208 #size-cells = <2>; 1209 device_type = "pci"; 1210 dma-coherent; 1211 apio-wins = <8>; 1212 ppio-wins = <8>; 1213 bus-range = <0x0 0xff>; 1214 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1215 msi-parent = <&its>; 1216 #interrupt-cells = <1>; 1217 interrupt-map-mask = <0 0 0 7>; 1218 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1219 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1220 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1221 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1222 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1223 status = "disabled"; 1224 }; 1225 1226 pcie5: pcie@3800000 { 1227 compatible = "fsl,lx2160a-pcie"; 1228 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */ 1229 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */ 1230 reg-names = "csr_axi_slave", "config_axi_slave"; 1231 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1232 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1233 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1234 interrupt-names = "aer", "pme", "intr"; 1235 #address-cells = <3>; 1236 #size-cells = <2>; 1237 device_type = "pci"; 1238 dma-coherent; 1239 apio-wins = <256>; 1240 ppio-wins = <24>; 1241 bus-range = <0x0 0xff>; 1242 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1243 msi-parent = <&its>; 1244 #interrupt-cells = <1>; 1245 interrupt-map-mask = <0 0 0 7>; 1246 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1247 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1248 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1249 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1250 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1251 status = "disabled"; 1252 }; 1253 1254 pcie6: pcie@3900000 { 1255 compatible = "fsl,lx2160a-pcie"; 1256 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */ 1257 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */ 1258 reg-names = "csr_axi_slave", "config_axi_slave"; 1259 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1260 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1261 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1262 interrupt-names = "aer", "pme", "intr"; 1263 #address-cells = <3>; 1264 #size-cells = <2>; 1265 device_type = "pci"; 1266 dma-coherent; 1267 apio-wins = <8>; 1268 ppio-wins = <8>; 1269 bus-range = <0x0 0xff>; 1270 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1271 msi-parent = <&its>; 1272 #interrupt-cells = <1>; 1273 interrupt-map-mask = <0 0 0 7>; 1274 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1275 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1276 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1277 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1278 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 1279 status = "disabled"; 1280 }; 1281 1282 smmu: iommu@5000000 { 1283 compatible = "arm,mmu-500"; 1284 reg = <0 0x5000000 0 0x800000>; 1285 #iommu-cells = <1>; 1286 #global-interrupts = <14>; 1287 // global secure fault 1288 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1289 // combined secure 1290 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1291 // global non-secure fault 1292 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1293 // combined non-secure 1294 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1295 // performance counter interrupts 0-9 1296 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1306 // per context interrupt, 64 interrupts 1307 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1371 dma-coherent; 1372 }; 1373 1374 console@8340020 { 1375 compatible = "fsl,dpaa2-console"; 1376 reg = <0x00000000 0x08340020 0 0x2>; 1377 }; 1378 1379 ptp-timer@8b95000 { 1380 compatible = "fsl,dpaa2-ptp"; 1381 reg = <0x0 0x8b95000 0x0 0x100>; 1382 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1383 QORIQ_CLK_PLL_DIV(2)>; 1384 little-endian; 1385 fsl,extts-fifo; 1386 }; 1387 1388 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 1389 emdio1: mdio@8b96000 { 1390 compatible = "fsl,fman-memac-mdio"; 1391 reg = <0x0 0x8b96000 0x0 0x1000>; 1392 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1393 #address-cells = <1>; 1394 #size-cells = <0>; 1395 little-endian; 1396 clock-frequency = <2500000>; 1397 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1398 QORIQ_CLK_PLL_DIV(2)>; 1399 status = "disabled"; 1400 }; 1401 1402 emdio2: mdio@8b97000 { 1403 compatible = "fsl,fman-memac-mdio"; 1404 reg = <0x0 0x8b97000 0x0 0x1000>; 1405 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1406 little-endian; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 clock-frequency = <2500000>; 1410 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1411 QORIQ_CLK_PLL_DIV(2)>; 1412 status = "disabled"; 1413 }; 1414 1415 pcs_mdio1: mdio@8c07000 { 1416 compatible = "fsl,fman-memac-mdio"; 1417 reg = <0x0 0x8c07000 0x0 0x1000>; 1418 little-endian; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 status = "disabled"; 1422 1423 pcs1: ethernet-phy@0 { 1424 reg = <0>; 1425 }; 1426 }; 1427 1428 pcs_mdio2: mdio@8c0b000 { 1429 compatible = "fsl,fman-memac-mdio"; 1430 reg = <0x0 0x8c0b000 0x0 0x1000>; 1431 little-endian; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 status = "disabled"; 1435 1436 pcs2: ethernet-phy@0 { 1437 reg = <0>; 1438 }; 1439 }; 1440 1441 pcs_mdio3: mdio@8c0f000 { 1442 compatible = "fsl,fman-memac-mdio"; 1443 reg = <0x0 0x8c0f000 0x0 0x1000>; 1444 little-endian; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 status = "disabled"; 1448 1449 pcs3: ethernet-phy@0 { 1450 reg = <0>; 1451 }; 1452 }; 1453 1454 pcs_mdio4: mdio@8c13000 { 1455 compatible = "fsl,fman-memac-mdio"; 1456 reg = <0x0 0x8c13000 0x0 0x1000>; 1457 little-endian; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 status = "disabled"; 1461 1462 pcs4: ethernet-phy@0 { 1463 reg = <0>; 1464 }; 1465 }; 1466 1467 pcs_mdio5: mdio@8c17000 { 1468 compatible = "fsl,fman-memac-mdio"; 1469 reg = <0x0 0x8c17000 0x0 0x1000>; 1470 little-endian; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 status = "disabled"; 1474 1475 pcs5: ethernet-phy@0 { 1476 reg = <0>; 1477 }; 1478 }; 1479 1480 pcs_mdio6: mdio@8c1b000 { 1481 compatible = "fsl,fman-memac-mdio"; 1482 reg = <0x0 0x8c1b000 0x0 0x1000>; 1483 little-endian; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 status = "disabled"; 1487 1488 pcs6: ethernet-phy@0 { 1489 reg = <0>; 1490 }; 1491 }; 1492 1493 pcs_mdio7: mdio@8c1f000 { 1494 compatible = "fsl,fman-memac-mdio"; 1495 reg = <0x0 0x8c1f000 0x0 0x1000>; 1496 little-endian; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 1501 pcs7: ethernet-phy@0 { 1502 reg = <0>; 1503 }; 1504 }; 1505 1506 pcs_mdio8: mdio@8c23000 { 1507 compatible = "fsl,fman-memac-mdio"; 1508 reg = <0x0 0x8c23000 0x0 0x1000>; 1509 little-endian; 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 status = "disabled"; 1513 1514 pcs8: ethernet-phy@0 { 1515 reg = <0>; 1516 }; 1517 }; 1518 1519 pcs_mdio9: mdio@8c27000 { 1520 compatible = "fsl,fman-memac-mdio"; 1521 reg = <0x0 0x8c27000 0x0 0x1000>; 1522 little-endian; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 status = "disabled"; 1526 1527 pcs9: ethernet-phy@0 { 1528 reg = <0>; 1529 }; 1530 }; 1531 1532 pcs_mdio10: mdio@8c2b000 { 1533 compatible = "fsl,fman-memac-mdio"; 1534 reg = <0x0 0x8c2b000 0x0 0x1000>; 1535 little-endian; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 status = "disabled"; 1539 1540 pcs10: ethernet-phy@0 { 1541 reg = <0>; 1542 }; 1543 }; 1544 1545 pcs_mdio11: mdio@8c2f000 { 1546 compatible = "fsl,fman-memac-mdio"; 1547 reg = <0x0 0x8c2f000 0x0 0x1000>; 1548 little-endian; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 status = "disabled"; 1552 1553 pcs11: ethernet-phy@0 { 1554 reg = <0>; 1555 }; 1556 }; 1557 1558 pcs_mdio12: mdio@8c33000 { 1559 compatible = "fsl,fman-memac-mdio"; 1560 reg = <0x0 0x8c33000 0x0 0x1000>; 1561 little-endian; 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 status = "disabled"; 1565 1566 pcs12: ethernet-phy@0 { 1567 reg = <0>; 1568 }; 1569 }; 1570 1571 pcs_mdio13: mdio@8c37000 { 1572 compatible = "fsl,fman-memac-mdio"; 1573 reg = <0x0 0x8c37000 0x0 0x1000>; 1574 little-endian; 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 status = "disabled"; 1578 1579 pcs13: ethernet-phy@0 { 1580 reg = <0>; 1581 }; 1582 }; 1583 1584 pcs_mdio14: mdio@8c3b000 { 1585 compatible = "fsl,fman-memac-mdio"; 1586 reg = <0x0 0x8c3b000 0x0 0x1000>; 1587 little-endian; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 status = "disabled"; 1591 1592 pcs14: ethernet-phy@0 { 1593 reg = <0>; 1594 }; 1595 }; 1596 1597 pcs_mdio15: mdio@8c3f000 { 1598 compatible = "fsl,fman-memac-mdio"; 1599 reg = <0x0 0x8c3f000 0x0 0x1000>; 1600 little-endian; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 status = "disabled"; 1604 1605 pcs15: ethernet-phy@0 { 1606 reg = <0>; 1607 }; 1608 }; 1609 1610 pcs_mdio16: mdio@8c43000 { 1611 compatible = "fsl,fman-memac-mdio"; 1612 reg = <0x0 0x8c43000 0x0 0x1000>; 1613 little-endian; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 status = "disabled"; 1617 1618 pcs16: ethernet-phy@0 { 1619 reg = <0>; 1620 }; 1621 }; 1622 1623 pcs_mdio17: mdio@8c47000 { 1624 compatible = "fsl,fman-memac-mdio"; 1625 reg = <0x0 0x8c47000 0x0 0x1000>; 1626 little-endian; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 1631 pcs17: ethernet-phy@0 { 1632 reg = <0>; 1633 }; 1634 }; 1635 1636 pcs_mdio18: mdio@8c4b000 { 1637 compatible = "fsl,fman-memac-mdio"; 1638 reg = <0x0 0x8c4b000 0x0 0x1000>; 1639 little-endian; 1640 #address-cells = <1>; 1641 #size-cells = <0>; 1642 status = "disabled"; 1643 1644 pcs18: ethernet-phy@0 { 1645 reg = <0>; 1646 }; 1647 }; 1648 1649 fsl_mc: fsl-mc@80c000000 { 1650 compatible = "fsl,qoriq-mc"; 1651 reg = <0x00000008 0x0c000000 0 0x40>, 1652 <0x00000000 0x08340000 0 0x40000>; 1653 msi-parent = <&its>; 1654 /* iommu-map property is fixed up by u-boot */ 1655 iommu-map = <0 &smmu 0 0>; 1656 dma-coherent; 1657 #address-cells = <3>; 1658 #size-cells = <1>; 1659 1660 /* 1661 * Region type 0x0 - MC portals 1662 * Region type 0x1 - QBMAN portals 1663 */ 1664 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1665 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1666 1667 /* 1668 * Define the maximum number of MACs present on the SoC. 1669 */ 1670 dpmacs { 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 1674 dpmac1: ethernet@1 { 1675 compatible = "fsl,qoriq-mc-dpmac"; 1676 reg = <0x1>; 1677 pcs-handle = <&pcs1>; 1678 }; 1679 1680 dpmac2: ethernet@2 { 1681 compatible = "fsl,qoriq-mc-dpmac"; 1682 reg = <0x2>; 1683 pcs-handle = <&pcs2>; 1684 }; 1685 1686 dpmac3: ethernet@3 { 1687 compatible = "fsl,qoriq-mc-dpmac"; 1688 reg = <0x3>; 1689 pcs-handle = <&pcs3>; 1690 }; 1691 1692 dpmac4: ethernet@4 { 1693 compatible = "fsl,qoriq-mc-dpmac"; 1694 reg = <0x4>; 1695 pcs-handle = <&pcs4>; 1696 }; 1697 1698 dpmac5: ethernet@5 { 1699 compatible = "fsl,qoriq-mc-dpmac"; 1700 reg = <0x5>; 1701 pcs-handle = <&pcs5>; 1702 }; 1703 1704 dpmac6: ethernet@6 { 1705 compatible = "fsl,qoriq-mc-dpmac"; 1706 reg = <0x6>; 1707 pcs-handle = <&pcs6>; 1708 }; 1709 1710 dpmac7: ethernet@7 { 1711 compatible = "fsl,qoriq-mc-dpmac"; 1712 reg = <0x7>; 1713 pcs-handle = <&pcs7>; 1714 }; 1715 1716 dpmac8: ethernet@8 { 1717 compatible = "fsl,qoriq-mc-dpmac"; 1718 reg = <0x8>; 1719 pcs-handle = <&pcs8>; 1720 }; 1721 1722 dpmac9: ethernet@9 { 1723 compatible = "fsl,qoriq-mc-dpmac"; 1724 reg = <0x9>; 1725 pcs-handle = <&pcs9>; 1726 }; 1727 1728 dpmac10: ethernet@a { 1729 compatible = "fsl,qoriq-mc-dpmac"; 1730 reg = <0xa>; 1731 pcs-handle = <&pcs10>; 1732 }; 1733 1734 dpmac11: ethernet@b { 1735 compatible = "fsl,qoriq-mc-dpmac"; 1736 reg = <0xb>; 1737 pcs-handle = <&pcs11>; 1738 }; 1739 1740 dpmac12: ethernet@c { 1741 compatible = "fsl,qoriq-mc-dpmac"; 1742 reg = <0xc>; 1743 pcs-handle = <&pcs12>; 1744 }; 1745 1746 dpmac13: ethernet@d { 1747 compatible = "fsl,qoriq-mc-dpmac"; 1748 reg = <0xd>; 1749 pcs-handle = <&pcs13>; 1750 }; 1751 1752 dpmac14: ethernet@e { 1753 compatible = "fsl,qoriq-mc-dpmac"; 1754 reg = <0xe>; 1755 pcs-handle = <&pcs14>; 1756 }; 1757 1758 dpmac15: ethernet@f { 1759 compatible = "fsl,qoriq-mc-dpmac"; 1760 reg = <0xf>; 1761 pcs-handle = <&pcs15>; 1762 }; 1763 1764 dpmac16: ethernet@10 { 1765 compatible = "fsl,qoriq-mc-dpmac"; 1766 reg = <0x10>; 1767 pcs-handle = <&pcs16>; 1768 }; 1769 1770 dpmac17: ethernet@11 { 1771 compatible = "fsl,qoriq-mc-dpmac"; 1772 reg = <0x11>; 1773 pcs-handle = <&pcs17>; 1774 }; 1775 1776 dpmac18: ethernet@12 { 1777 compatible = "fsl,qoriq-mc-dpmac"; 1778 reg = <0x12>; 1779 pcs-handle = <&pcs18>; 1780 }; 1781 }; 1782 }; 1783 }; 1784 1785 firmware { 1786 optee: optee { 1787 compatible = "linaro,optee-tz"; 1788 method = "smc"; 1789 status = "disabled"; 1790 }; 1791 }; 1792}; 1793