1/* 2 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 3 * 4 * Copyright (C) 2014-2016, Freescale Semiconductor 5 * 6 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 7 * Bhupesh Sharma <bhupesh.sharma@freescale.com> 8 * 9 * This file is dual-licensed: you can use it either under the terms 10 * of the GPLv2 or the X11 license, at your option. Note that this dual 11 * licensing only applies to this file, and not this project as a 12 * whole. 13 * 14 * a) This library is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of the 17 * License, or (at your option) any later version. 18 * 19 * This library is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "fsl-ls208xa.dtsi" 49 50&cpu { 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a57"; 54 reg = <0x0>; 55 clocks = <&clockgen 1 0>; 56 next-level-cache = <&cluster0_l2>; 57 #cooling-cells = <2>; 58 }; 59 60 cpu1: cpu@1 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a57"; 63 reg = <0x1>; 64 clocks = <&clockgen 1 0>; 65 next-level-cache = <&cluster0_l2>; 66 }; 67 68 cpu2: cpu@100 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a57"; 71 reg = <0x100>; 72 clocks = <&clockgen 1 1>; 73 next-level-cache = <&cluster1_l2>; 74 #cooling-cells = <2>; 75 }; 76 77 cpu3: cpu@101 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a57"; 80 reg = <0x101>; 81 clocks = <&clockgen 1 1>; 82 next-level-cache = <&cluster1_l2>; 83 }; 84 85 cpu4: cpu@200 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a57"; 88 reg = <0x200>; 89 clocks = <&clockgen 1 2>; 90 next-level-cache = <&cluster2_l2>; 91 #cooling-cells = <2>; 92 }; 93 94 cpu5: cpu@201 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a57"; 97 reg = <0x201>; 98 clocks = <&clockgen 1 2>; 99 next-level-cache = <&cluster2_l2>; 100 }; 101 102 cpu6: cpu@300 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a57"; 105 reg = <0x300>; 106 clocks = <&clockgen 1 3>; 107 next-level-cache = <&cluster3_l2>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu7: cpu@301 { 112 device_type = "cpu"; 113 compatible = "arm,cortex-a57"; 114 reg = <0x301>; 115 clocks = <&clockgen 1 3>; 116 next-level-cache = <&cluster3_l2>; 117 }; 118 119 cluster0_l2: l2-cache0 { 120 compatible = "cache"; 121 }; 122 123 cluster1_l2: l2-cache1 { 124 compatible = "cache"; 125 }; 126 127 cluster2_l2: l2-cache2 { 128 compatible = "cache"; 129 }; 130 131 cluster3_l2: l2-cache3 { 132 compatible = "cache"; 133 }; 134}; 135 136&pcie1 { 137 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 138 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ 139 140 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ 141 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 142}; 143 144&pcie2 { 145 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 146 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ 147 148 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ 149 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 150}; 151 152&pcie3 { 153 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 154 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ 155 156 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ 157 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 158}; 159 160&pcie4 { 161 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 162 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ 163 164 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ 165 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 166}; 167