1/* 2 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 3 * 4 * Copyright (C) 2014-2015, Freescale Semiconductor 5 * 6 * Bhupesh Sharma <bhupesh.sharma@freescale.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPLv2 or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This library is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This library is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47/ { 48 compatible = "fsl,ls2080a"; 49 interrupt-parent = <&gic>; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 53 cpus { 54 #address-cells = <2>; 55 #size-cells = <0>; 56 57 /* 58 * We expect the enable-method for cpu's to be "psci", but this 59 * is dependent on the SoC FW, which will fill this in. 60 * 61 * Currently supported enable-method is psci v0.2 62 */ 63 64 /* We have 4 clusters having 2 Cortex-A57 cores each */ 65 cpu@0 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a57"; 68 reg = <0x0 0x0>; 69 clocks = <&clockgen 1 0>; 70 }; 71 72 cpu@1 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a57"; 75 reg = <0x0 0x1>; 76 clocks = <&clockgen 1 0>; 77 }; 78 79 cpu@100 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a57"; 82 reg = <0x0 0x100>; 83 clocks = <&clockgen 1 1>; 84 }; 85 86 cpu@101 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a57"; 89 reg = <0x0 0x101>; 90 clocks = <&clockgen 1 1>; 91 }; 92 93 cpu@200 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a57"; 96 reg = <0x0 0x200>; 97 clocks = <&clockgen 1 2>; 98 }; 99 100 cpu@201 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a57"; 103 reg = <0x0 0x201>; 104 clocks = <&clockgen 1 2>; 105 }; 106 107 cpu@300 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a57"; 110 reg = <0x0 0x300>; 111 clocks = <&clockgen 1 3>; 112 }; 113 114 cpu@301 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a57"; 117 reg = <0x0 0x301>; 118 clocks = <&clockgen 1 3>; 119 }; 120 }; 121 122 memory@80000000 { 123 device_type = "memory"; 124 reg = <0x00000000 0x80000000 0 0x80000000>; 125 /* DRAM space - 1, size : 2 GB DRAM */ 126 }; 127 128 sysclk: sysclk { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <100000000>; 132 clock-output-names = "sysclk"; 133 }; 134 135 gic: interrupt-controller@6000000 { 136 compatible = "arm,gic-v3"; 137 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 138 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ 139 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 140 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 141 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 142 #interrupt-cells = <3>; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges; 146 interrupt-controller; 147 interrupts = <1 9 0x4>; 148 149 its: gic-its@6020000 { 150 compatible = "arm,gic-v3-its"; 151 msi-controller; 152 reg = <0x0 0x6020000 0 0x20000>; 153 }; 154 }; 155 156 rstcr: syscon@1e60000 { 157 compatible = "fsl,ls2080a-rstcr", "syscon"; 158 reg = <0x0 0x1e60000 0x0 0x4>; 159 }; 160 161 reboot { 162 compatible ="syscon-reboot"; 163 regmap = <&rstcr>; 164 offset = <0x0>; 165 mask = <0x2>; 166 }; 167 168 timer { 169 compatible = "arm,armv8-timer"; 170 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 171 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */ 172 <1 11 0x8>, /* Virtual PPI, active-low */ 173 <1 10 0x8>; /* Hypervisor PPI, active-low */ 174 }; 175 176 pmu { 177 compatible = "arm,armv8-pmuv3"; 178 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 179 }; 180 181 soc { 182 compatible = "simple-bus"; 183 #address-cells = <2>; 184 #size-cells = <2>; 185 ranges; 186 187 clockgen: clocking@1300000 { 188 compatible = "fsl,ls2080a-clockgen"; 189 reg = <0 0x1300000 0 0xa0000>; 190 #clock-cells = <2>; 191 clocks = <&sysclk>; 192 }; 193 194 serial0: serial@21c0500 { 195 compatible = "fsl,ns16550", "ns16550a"; 196 reg = <0x0 0x21c0500 0x0 0x100>; 197 clocks = <&clockgen 4 3>; 198 interrupts = <0 32 0x4>; /* Level high type */ 199 }; 200 201 serial1: serial@21c0600 { 202 compatible = "fsl,ns16550", "ns16550a"; 203 reg = <0x0 0x21c0600 0x0 0x100>; 204 clocks = <&clockgen 4 3>; 205 interrupts = <0 32 0x4>; /* Level high type */ 206 }; 207 208 cluster1_core0_watchdog: wdt@c000000 { 209 compatible = "arm,sp805-wdt", "arm,primecell"; 210 reg = <0x0 0xc000000 0x0 0x1000>; 211 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 212 clock-names = "apb_pclk", "wdog_clk"; 213 }; 214 215 cluster1_core1_watchdog: wdt@c010000 { 216 compatible = "arm,sp805-wdt", "arm,primecell"; 217 reg = <0x0 0xc010000 0x0 0x1000>; 218 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 219 clock-names = "apb_pclk", "wdog_clk"; 220 }; 221 222 cluster2_core0_watchdog: wdt@c100000 { 223 compatible = "arm,sp805-wdt", "arm,primecell"; 224 reg = <0x0 0xc100000 0x0 0x1000>; 225 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 226 clock-names = "apb_pclk", "wdog_clk"; 227 }; 228 229 cluster2_core1_watchdog: wdt@c110000 { 230 compatible = "arm,sp805-wdt", "arm,primecell"; 231 reg = <0x0 0xc110000 0x0 0x1000>; 232 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 233 clock-names = "apb_pclk", "wdog_clk"; 234 }; 235 236 cluster3_core0_watchdog: wdt@c200000 { 237 compatible = "arm,sp805-wdt", "arm,primecell"; 238 reg = <0x0 0xc200000 0x0 0x1000>; 239 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 240 clock-names = "apb_pclk", "wdog_clk"; 241 }; 242 243 cluster3_core1_watchdog: wdt@c210000 { 244 compatible = "arm,sp805-wdt", "arm,primecell"; 245 reg = <0x0 0xc210000 0x0 0x1000>; 246 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 247 clock-names = "apb_pclk", "wdog_clk"; 248 }; 249 250 cluster4_core0_watchdog: wdt@c300000 { 251 compatible = "arm,sp805-wdt", "arm,primecell"; 252 reg = <0x0 0xc300000 0x0 0x1000>; 253 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 254 clock-names = "apb_pclk", "wdog_clk"; 255 }; 256 257 cluster4_core1_watchdog: wdt@c310000 { 258 compatible = "arm,sp805-wdt", "arm,primecell"; 259 reg = <0x0 0xc310000 0x0 0x1000>; 260 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 261 clock-names = "apb_pclk", "wdog_clk"; 262 }; 263 264 fsl_mc: fsl-mc@80c000000 { 265 compatible = "fsl,qoriq-mc"; 266 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 267 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 268 msi-parent = <&its>; 269 #address-cells = <3>; 270 #size-cells = <1>; 271 272 /* 273 * Region type 0x0 - MC portals 274 * Region type 0x1 - QBMAN portals 275 */ 276 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 277 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 278 279 /* 280 * Define the maximum number of MACs present on the SoC. 281 */ 282 dpmacs { 283 #address-cells = <1>; 284 #size-cells = <0>; 285 286 dpmac1: dpmac@1 { 287 compatible = "fsl,qoriq-mc-dpmac"; 288 reg = <0x1>; 289 }; 290 291 dpmac2: dpmac@2 { 292 compatible = "fsl,qoriq-mc-dpmac"; 293 reg = <0x2>; 294 }; 295 296 dpmac3: dpmac@3 { 297 compatible = "fsl,qoriq-mc-dpmac"; 298 reg = <0x3>; 299 }; 300 301 dpmac4: dpmac@4 { 302 compatible = "fsl,qoriq-mc-dpmac"; 303 reg = <0x4>; 304 }; 305 306 dpmac5: dpmac@5 { 307 compatible = "fsl,qoriq-mc-dpmac"; 308 reg = <0x5>; 309 }; 310 311 dpmac6: dpmac@6 { 312 compatible = "fsl,qoriq-mc-dpmac"; 313 reg = <0x6>; 314 }; 315 316 dpmac7: dpmac@7 { 317 compatible = "fsl,qoriq-mc-dpmac"; 318 reg = <0x7>; 319 }; 320 321 dpmac8: dpmac@8 { 322 compatible = "fsl,qoriq-mc-dpmac"; 323 reg = <0x8>; 324 }; 325 326 dpmac9: dpmac@9 { 327 compatible = "fsl,qoriq-mc-dpmac"; 328 reg = <0x9>; 329 }; 330 331 dpmac10: dpmac@a { 332 compatible = "fsl,qoriq-mc-dpmac"; 333 reg = <0xa>; 334 }; 335 336 dpmac11: dpmac@b { 337 compatible = "fsl,qoriq-mc-dpmac"; 338 reg = <0xb>; 339 }; 340 341 dpmac12: dpmac@c { 342 compatible = "fsl,qoriq-mc-dpmac"; 343 reg = <0xc>; 344 }; 345 346 dpmac13: dpmac@d { 347 compatible = "fsl,qoriq-mc-dpmac"; 348 reg = <0xd>; 349 }; 350 351 dpmac14: dpmac@e { 352 compatible = "fsl,qoriq-mc-dpmac"; 353 reg = <0xe>; 354 }; 355 356 dpmac15: dpmac@f { 357 compatible = "fsl,qoriq-mc-dpmac"; 358 reg = <0xf>; 359 }; 360 361 dpmac16: dpmac@10 { 362 compatible = "fsl,qoriq-mc-dpmac"; 363 reg = <0x10>; 364 }; 365 }; 366 }; 367 368 smmu: iommu@5000000 { 369 compatible = "arm,mmu-500"; 370 reg = <0 0x5000000 0 0x800000>; 371 #global-interrupts = <12>; 372 interrupts = <0 13 4>, /* global secure fault */ 373 <0 14 4>, /* combined secure interrupt */ 374 <0 15 4>, /* global non-secure fault */ 375 <0 16 4>, /* combined non-secure interrupt */ 376 /* performance counter interrupts 0-7 */ 377 <0 211 4>, <0 212 4>, 378 <0 213 4>, <0 214 4>, 379 <0 215 4>, <0 216 4>, 380 <0 217 4>, <0 218 4>, 381 /* per context interrupt, 64 interrupts */ 382 <0 146 4>, <0 147 4>, 383 <0 148 4>, <0 149 4>, 384 <0 150 4>, <0 151 4>, 385 <0 152 4>, <0 153 4>, 386 <0 154 4>, <0 155 4>, 387 <0 156 4>, <0 157 4>, 388 <0 158 4>, <0 159 4>, 389 <0 160 4>, <0 161 4>, 390 <0 162 4>, <0 163 4>, 391 <0 164 4>, <0 165 4>, 392 <0 166 4>, <0 167 4>, 393 <0 168 4>, <0 169 4>, 394 <0 170 4>, <0 171 4>, 395 <0 172 4>, <0 173 4>, 396 <0 174 4>, <0 175 4>, 397 <0 176 4>, <0 177 4>, 398 <0 178 4>, <0 179 4>, 399 <0 180 4>, <0 181 4>, 400 <0 182 4>, <0 183 4>, 401 <0 184 4>, <0 185 4>, 402 <0 186 4>, <0 187 4>, 403 <0 188 4>, <0 189 4>, 404 <0 190 4>, <0 191 4>, 405 <0 192 4>, <0 193 4>, 406 <0 194 4>, <0 195 4>, 407 <0 196 4>, <0 197 4>, 408 <0 198 4>, <0 199 4>, 409 <0 200 4>, <0 201 4>, 410 <0 202 4>, <0 203 4>, 411 <0 204 4>, <0 205 4>, 412 <0 206 4>, <0 207 4>, 413 <0 208 4>, <0 209 4>; 414 mmu-masters = <&fsl_mc 0x300 0>; 415 }; 416 417 dspi: dspi@2100000 { 418 status = "disabled"; 419 compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <0x0 0x2100000 0x0 0x10000>; 423 interrupts = <0 26 0x4>; /* Level high type */ 424 clocks = <&clockgen 4 3>; 425 clock-names = "dspi"; 426 spi-num-chipselects = <5>; 427 bus-num = <0>; 428 }; 429 430 esdhc: esdhc@2140000 { 431 status = "disabled"; 432 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 433 reg = <0x0 0x2140000 0x0 0x10000>; 434 interrupts = <0 28 0x4>; /* Level high type */ 435 clock-frequency = <0>; /* Updated by bootloader */ 436 voltage-ranges = <1800 1800 3300 3300>; 437 sdhci,auto-cmd12; 438 little-endian; 439 bus-width = <4>; 440 }; 441 442 gpio0: gpio@2300000 { 443 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 444 reg = <0x0 0x2300000 0x0 0x10000>; 445 interrupts = <0 36 0x4>; /* Level high type */ 446 gpio-controller; 447 little-endian; 448 #gpio-cells = <2>; 449 interrupt-controller; 450 #interrupt-cells = <2>; 451 }; 452 453 gpio1: gpio@2310000 { 454 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 455 reg = <0x0 0x2310000 0x0 0x10000>; 456 interrupts = <0 36 0x4>; /* Level high type */ 457 gpio-controller; 458 little-endian; 459 #gpio-cells = <2>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 }; 463 464 gpio2: gpio@2320000 { 465 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 466 reg = <0x0 0x2320000 0x0 0x10000>; 467 interrupts = <0 37 0x4>; /* Level high type */ 468 gpio-controller; 469 little-endian; 470 #gpio-cells = <2>; 471 interrupt-controller; 472 #interrupt-cells = <2>; 473 }; 474 475 gpio3: gpio@2330000 { 476 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 477 reg = <0x0 0x2330000 0x0 0x10000>; 478 interrupts = <0 37 0x4>; /* Level high type */ 479 gpio-controller; 480 little-endian; 481 #gpio-cells = <2>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 }; 485 486 i2c0: i2c@2000000 { 487 status = "disabled"; 488 compatible = "fsl,vf610-i2c"; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 reg = <0x0 0x2000000 0x0 0x10000>; 492 interrupts = <0 34 0x4>; /* Level high type */ 493 clock-names = "i2c"; 494 clocks = <&clockgen 4 3>; 495 }; 496 497 i2c1: i2c@2010000 { 498 status = "disabled"; 499 compatible = "fsl,vf610-i2c"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 reg = <0x0 0x2010000 0x0 0x10000>; 503 interrupts = <0 34 0x4>; /* Level high type */ 504 clock-names = "i2c"; 505 clocks = <&clockgen 4 3>; 506 }; 507 508 i2c2: i2c@2020000 { 509 status = "disabled"; 510 compatible = "fsl,vf610-i2c"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 reg = <0x0 0x2020000 0x0 0x10000>; 514 interrupts = <0 35 0x4>; /* Level high type */ 515 clock-names = "i2c"; 516 clocks = <&clockgen 4 3>; 517 }; 518 519 i2c3: i2c@2030000 { 520 status = "disabled"; 521 compatible = "fsl,vf610-i2c"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 reg = <0x0 0x2030000 0x0 0x10000>; 525 interrupts = <0 35 0x4>; /* Level high type */ 526 clock-names = "i2c"; 527 clocks = <&clockgen 4 3>; 528 }; 529 530 ifc: ifc@2240000 { 531 compatible = "fsl,ifc", "simple-bus"; 532 reg = <0x0 0x2240000 0x0 0x20000>; 533 interrupts = <0 21 0x4>; /* Level high type */ 534 little-endian; 535 #address-cells = <2>; 536 #size-cells = <1>; 537 538 ranges = <0 0 0x5 0x80000000 0x08000000 539 2 0 0x5 0x30000000 0x00010000 540 3 0 0x5 0x20000000 0x00010000>; 541 }; 542 543 qspi: quadspi@20c0000 { 544 status = "disabled"; 545 compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 reg = <0x0 0x20c0000 0x0 0x10000>, 549 <0x0 0x20000000 0x0 0x10000000>; 550 reg-names = "QuadSPI", "QuadSPI-memory"; 551 interrupts = <0 25 0x4>; /* Level high type */ 552 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 553 clock-names = "qspi_en", "qspi"; 554 }; 555 556 pcie@3400000 { 557 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 558 "snps,dw-pcie"; 559 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 560 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ 561 reg-names = "regs", "config"; 562 interrupts = <0 108 0x4>; /* Level high type */ 563 interrupt-names = "intr"; 564 #address-cells = <3>; 565 #size-cells = <2>; 566 device_type = "pci"; 567 num-lanes = <4>; 568 bus-range = <0x0 0xff>; 569 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ 570 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 571 msi-parent = <&its>; 572 #interrupt-cells = <1>; 573 interrupt-map-mask = <0 0 0 7>; 574 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, 575 <0000 0 0 2 &gic 0 0 0 110 4>, 576 <0000 0 0 3 &gic 0 0 0 111 4>, 577 <0000 0 0 4 &gic 0 0 0 112 4>; 578 }; 579 580 pcie@3500000 { 581 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 582 "snps,dw-pcie"; 583 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 584 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ 585 reg-names = "regs", "config"; 586 interrupts = <0 113 0x4>; /* Level high type */ 587 interrupt-names = "intr"; 588 #address-cells = <3>; 589 #size-cells = <2>; 590 device_type = "pci"; 591 num-lanes = <4>; 592 bus-range = <0x0 0xff>; 593 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ 594 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 595 msi-parent = <&its>; 596 #interrupt-cells = <1>; 597 interrupt-map-mask = <0 0 0 7>; 598 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, 599 <0000 0 0 2 &gic 0 0 0 115 4>, 600 <0000 0 0 3 &gic 0 0 0 116 4>, 601 <0000 0 0 4 &gic 0 0 0 117 4>; 602 }; 603 604 pcie@3600000 { 605 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 606 "snps,dw-pcie"; 607 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 608 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ 609 reg-names = "regs", "config"; 610 interrupts = <0 118 0x4>; /* Level high type */ 611 interrupt-names = "intr"; 612 #address-cells = <3>; 613 #size-cells = <2>; 614 device_type = "pci"; 615 num-lanes = <8>; 616 bus-range = <0x0 0xff>; 617 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ 618 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 619 msi-parent = <&its>; 620 #interrupt-cells = <1>; 621 interrupt-map-mask = <0 0 0 7>; 622 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, 623 <0000 0 0 2 &gic 0 0 0 120 4>, 624 <0000 0 0 3 &gic 0 0 0 121 4>, 625 <0000 0 0 4 &gic 0 0 0 122 4>; 626 }; 627 628 pcie@3700000 { 629 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", 630 "snps,dw-pcie"; 631 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 632 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ 633 reg-names = "regs", "config"; 634 interrupts = <0 123 0x4>; /* Level high type */ 635 interrupt-names = "intr"; 636 #address-cells = <3>; 637 #size-cells = <2>; 638 device_type = "pci"; 639 num-lanes = <4>; 640 bus-range = <0x0 0xff>; 641 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ 642 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 643 msi-parent = <&its>; 644 #interrupt-cells = <1>; 645 interrupt-map-mask = <0 0 0 7>; 646 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, 647 <0000 0 0 2 &gic 0 0 0 125 4>, 648 <0000 0 0 3 &gic 0 0 0 126 4>, 649 <0000 0 0 4 &gic 0 0 0 127 4>; 650 }; 651 652 sata0: sata@3200000 { 653 status = "disabled"; 654 compatible = "fsl,ls2080a-ahci"; 655 reg = <0x0 0x3200000 0x0 0x10000>; 656 interrupts = <0 133 0x4>; /* Level high type */ 657 clocks = <&clockgen 4 3>; 658 }; 659 660 sata1: sata@3210000 { 661 status = "disabled"; 662 compatible = "fsl,ls2080a-ahci"; 663 reg = <0x0 0x3210000 0x0 0x10000>; 664 interrupts = <0 136 0x4>; /* Level high type */ 665 clocks = <&clockgen 4 3>; 666 }; 667 668 usb0: usb3@3100000 { 669 status = "disabled"; 670 compatible = "snps,dwc3"; 671 reg = <0x0 0x3100000 0x0 0x10000>; 672 interrupts = <0 80 0x4>; /* Level high type */ 673 dr_mode = "host"; 674 snps,quirk-frame-length-adjustment = <0x20>; 675 }; 676 677 usb1: usb3@3110000 { 678 status = "disabled"; 679 compatible = "snps,dwc3"; 680 reg = <0x0 0x3110000 0x0 0x10000>; 681 interrupts = <0 81 0x4>; /* Level high type */ 682 dr_mode = "host"; 683 snps,quirk-frame-length-adjustment = <0x20>; 684 }; 685 686 ccn@4000000 { 687 compatible = "arm,ccn-504"; 688 reg = <0x0 0x04000000 0x0 0x01000000>; 689 interrupts = <0 12 4>; 690 }; 691 }; 692}; 693