1/* 2 * Device Tree Include file for NXP Layerscape-1088A family SoC. 3 * 4 * Copyright 2017 NXP 5 * 6 * Harninder Rai <harninder.rai@nxp.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPLv2 or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This library is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This library is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively, 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use, 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/thermal/thermal.h> 48 49/ { 50 compatible = "fsl,ls1088a"; 51 interrupt-parent = <&gic>; 52 #address-cells = <2>; 53 #size-cells = <2>; 54 55 aliases { 56 crypto = &crypto; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 /* We have 2 clusters having 4 Cortex-A53 cores each */ 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0>; 68 clocks = <&clockgen 1 0>; 69 cpu-idle-states = <&CPU_PH20>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu1: cpu@1 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x1>; 77 clocks = <&clockgen 1 0>; 78 cpu-idle-states = <&CPU_PH20>; 79 }; 80 81 cpu2: cpu@2 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x2>; 85 clocks = <&clockgen 1 0>; 86 cpu-idle-states = <&CPU_PH20>; 87 }; 88 89 cpu3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 reg = <0x3>; 93 clocks = <&clockgen 1 0>; 94 cpu-idle-states = <&CPU_PH20>; 95 }; 96 97 cpu4: cpu@100 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x100>; 101 clocks = <&clockgen 1 1>; 102 cpu-idle-states = <&CPU_PH20>; 103 #cooling-cells = <2>; 104 }; 105 106 cpu5: cpu@101 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x101>; 110 clocks = <&clockgen 1 1>; 111 cpu-idle-states = <&CPU_PH20>; 112 }; 113 114 cpu6: cpu@102 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a53"; 117 reg = <0x102>; 118 clocks = <&clockgen 1 1>; 119 cpu-idle-states = <&CPU_PH20>; 120 }; 121 122 cpu7: cpu@103 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a53"; 125 reg = <0x103>; 126 clocks = <&clockgen 1 1>; 127 cpu-idle-states = <&CPU_PH20>; 128 }; 129 130 CPU_PH20: cpu-ph20 { 131 compatible = "arm,idle-state"; 132 idle-state-name = "PH20"; 133 arm,psci-suspend-param = <0x00010000>; 134 entry-latency-us = <1000>; 135 exit-latency-us = <1000>; 136 min-residency-us = <3000>; 137 }; 138 }; 139 140 gic: interrupt-controller@6000000 { 141 compatible = "arm,gic-v3"; 142 #interrupt-cells = <3>; 143 interrupt-controller; 144 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 145 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 146 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 147 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 148 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 149 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 150 #address-cells = <2>; 151 #size-cells = <2>; 152 ranges; 153 154 its: gic-its@6020000 { 155 compatible = "arm,gic-v3-its"; 156 msi-controller; 157 reg = <0x0 0x6020000 0 0x20000>; 158 }; 159 }; 160 161 timer { 162 compatible = "arm,armv8-timer"; 163 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 164 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 165 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 166 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 167 }; 168 169 fsl_mc: fsl-mc@80c000000 { 170 compatible = "fsl,qoriq-mc"; 171 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 172 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 173 msi-parent = <&its>; 174 #address-cells = <3>; 175 #size-cells = <1>; 176 177 /* 178 * Region type 0x0 - MC portals 179 * Region type 0x1 - QBMAN portals 180 */ 181 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 182 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 183 184 dpmacs { 185 #address-cells = <1>; 186 #size-cells = <0>; 187 188 dpmac1: dpmac@1 { 189 compatible = "fsl,qoriq-mc-dpmac"; 190 reg = <1>; 191 }; 192 193 dpmac2: dpmac@2 { 194 compatible = "fsl,qoriq-mc-dpmac"; 195 reg = <2>; 196 }; 197 198 dpmac3: dpmac@3 { 199 compatible = "fsl,qoriq-mc-dpmac"; 200 reg = <3>; 201 }; 202 203 dpmac4: dpmac@4 { 204 compatible = "fsl,qoriq-mc-dpmac"; 205 reg = <4>; 206 }; 207 208 dpmac5: dpmac@5 { 209 compatible = "fsl,qoriq-mc-dpmac"; 210 reg = <5>; 211 }; 212 213 dpmac6: dpmac@6 { 214 compatible = "fsl,qoriq-mc-dpmac"; 215 reg = <6>; 216 }; 217 218 dpmac7: dpmac@7 { 219 compatible = "fsl,qoriq-mc-dpmac"; 220 reg = <7>; 221 }; 222 223 dpmac8: dpmac@8 { 224 compatible = "fsl,qoriq-mc-dpmac"; 225 reg = <8>; 226 }; 227 228 dpmac9: dpmac@9 { 229 compatible = "fsl,qoriq-mc-dpmac"; 230 reg = <9>; 231 }; 232 233 dpmac10: dpmac@a { 234 compatible = "fsl,qoriq-mc-dpmac"; 235 reg = <0xa>; 236 }; 237 }; 238 }; 239 240 psci { 241 compatible = "arm,psci-0.2"; 242 method = "smc"; 243 }; 244 245 sysclk: sysclk { 246 compatible = "fixed-clock"; 247 #clock-cells = <0>; 248 clock-frequency = <100000000>; 249 clock-output-names = "sysclk"; 250 }; 251 252 soc { 253 compatible = "simple-bus"; 254 #address-cells = <2>; 255 #size-cells = <2>; 256 ranges; 257 258 clockgen: clocking@1300000 { 259 compatible = "fsl,ls1088a-clockgen"; 260 reg = <0 0x1300000 0 0xa0000>; 261 #clock-cells = <2>; 262 clocks = <&sysclk>; 263 }; 264 265 dcfg: dcfg@1e00000 { 266 compatible = "fsl,ls1088a-dcfg", "syscon"; 267 reg = <0x0 0x1e00000 0x0 0x10000>; 268 little-endian; 269 }; 270 271 tmu: tmu@1f80000 { 272 compatible = "fsl,qoriq-tmu"; 273 reg = <0x0 0x1f80000 0x0 0x10000>; 274 interrupts = <0 23 0x4>; 275 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 276 fsl,tmu-calibration = 277 /* Calibration data group 1 */ 278 <0x00000000 0x00000026 279 0x00000001 0x0000002d 280 0x00000002 0x00000032 281 0x00000003 0x00000039 282 0x00000004 0x0000003f 283 0x00000005 0x00000046 284 0x00000006 0x0000004d 285 0x00000007 0x00000054 286 0x00000008 0x0000005a 287 0x00000009 0x00000061 288 0x0000000a 0x0000006a 289 0x0000000b 0x00000071 290 /* Calibration data group 2 */ 291 0x00010000 0x00000025 292 0x00010001 0x0000002c 293 0x00010002 0x00000035 294 0x00010003 0x0000003d 295 0x00010004 0x00000045 296 0x00010005 0x0000004e 297 0x00010006 0x00000057 298 0x00010007 0x00000061 299 0x00010008 0x0000006b 300 0x00010009 0x00000076 301 /* Calibration data group 3 */ 302 0x00020000 0x00000029 303 0x00020001 0x00000033 304 0x00020002 0x0000003d 305 0x00020003 0x00000049 306 0x00020004 0x00000056 307 0x00020005 0x00000061 308 0x00020006 0x0000006d 309 /* Calibration data group 4 */ 310 0x00030000 0x00000021 311 0x00030001 0x0000002a 312 0x00030002 0x0000003c 313 0x00030003 0x0000004e>; 314 little-endian; 315 #thermal-sensor-cells = <1>; 316 }; 317 318 thermal-zones { 319 cpu_thermal: cpu-thermal { 320 polling-delay-passive = <1000>; 321 polling-delay = <5000>; 322 thermal-sensors = <&tmu 0>; 323 324 trips { 325 cpu_alert: cpu-alert { 326 temperature = <85000>; 327 hysteresis = <2000>; 328 type = "passive"; 329 }; 330 331 cpu_crit: cpu-crit { 332 temperature = <95000>; 333 hysteresis = <2000>; 334 type = "critical"; 335 }; 336 }; 337 338 cooling-maps { 339 map0 { 340 trip = <&cpu_alert>; 341 cooling-device = 342 <&cpu0 THERMAL_NO_LIMIT 343 THERMAL_NO_LIMIT>; 344 }; 345 346 map1 { 347 trip = <&cpu_alert>; 348 cooling-device = 349 <&cpu4 THERMAL_NO_LIMIT 350 THERMAL_NO_LIMIT>; 351 }; 352 }; 353 }; 354 }; 355 356 duart0: serial@21c0500 { 357 compatible = "fsl,ns16550", "ns16550a"; 358 reg = <0x0 0x21c0500 0x0 0x100>; 359 clocks = <&clockgen 4 3>; 360 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 361 status = "disabled"; 362 }; 363 364 duart1: serial@21c0600 { 365 compatible = "fsl,ns16550", "ns16550a"; 366 reg = <0x0 0x21c0600 0x0 0x100>; 367 clocks = <&clockgen 4 3>; 368 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 369 status = "disabled"; 370 }; 371 372 gpio0: gpio@2300000 { 373 compatible = "fsl,qoriq-gpio"; 374 reg = <0x0 0x2300000 0x0 0x10000>; 375 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 376 gpio-controller; 377 #gpio-cells = <2>; 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 }; 381 382 gpio1: gpio@2310000 { 383 compatible = "fsl,qoriq-gpio"; 384 reg = <0x0 0x2310000 0x0 0x10000>; 385 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 386 gpio-controller; 387 #gpio-cells = <2>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 }; 391 392 gpio2: gpio@2320000 { 393 compatible = "fsl,qoriq-gpio"; 394 reg = <0x0 0x2320000 0x0 0x10000>; 395 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 }; 401 402 gpio3: gpio@2330000 { 403 compatible = "fsl,qoriq-gpio"; 404 reg = <0x0 0x2330000 0x0 0x10000>; 405 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 406 gpio-controller; 407 #gpio-cells = <2>; 408 interrupt-controller; 409 #interrupt-cells = <2>; 410 }; 411 412 ifc: ifc@2240000 { 413 compatible = "fsl,ifc", "simple-bus"; 414 reg = <0x0 0x2240000 0x0 0x20000>; 415 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 416 little-endian; 417 #address-cells = <2>; 418 #size-cells = <1>; 419 status = "disabled"; 420 }; 421 422 i2c0: i2c@2000000 { 423 compatible = "fsl,vf610-i2c"; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 reg = <0x0 0x2000000 0x0 0x10000>; 427 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clockgen 4 3>; 429 status = "disabled"; 430 }; 431 432 i2c1: i2c@2010000 { 433 compatible = "fsl,vf610-i2c"; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 reg = <0x0 0x2010000 0x0 0x10000>; 437 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&clockgen 4 3>; 439 status = "disabled"; 440 }; 441 442 i2c2: i2c@2020000 { 443 compatible = "fsl,vf610-i2c"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 reg = <0x0 0x2020000 0x0 0x10000>; 447 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&clockgen 4 3>; 449 status = "disabled"; 450 }; 451 452 i2c3: i2c@2030000 { 453 compatible = "fsl,vf610-i2c"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 reg = <0x0 0x2030000 0x0 0x10000>; 457 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clockgen 4 3>; 459 status = "disabled"; 460 }; 461 462 esdhc: esdhc@2140000 { 463 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 464 reg = <0x0 0x2140000 0x0 0x10000>; 465 interrupts = <0 28 0x4>; /* Level high type */ 466 clock-frequency = <0>; 467 voltage-ranges = <1800 1800 3300 3300>; 468 sdhci,auto-cmd12; 469 little-endian; 470 bus-width = <4>; 471 status = "disabled"; 472 }; 473 474 usb0: usb3@3100000 { 475 compatible = "snps,dwc3"; 476 reg = <0x0 0x3100000 0x0 0x10000>; 477 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 478 dr_mode = "host"; 479 snps,quirk-frame-length-adjustment = <0x20>; 480 snps,dis_rxdet_inp3_quirk; 481 status = "disabled"; 482 }; 483 484 usb1: usb3@3110000 { 485 compatible = "snps,dwc3"; 486 reg = <0x0 0x3110000 0x0 0x10000>; 487 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 488 dr_mode = "host"; 489 snps,quirk-frame-length-adjustment = <0x20>; 490 snps,dis_rxdet_inp3_quirk; 491 status = "disabled"; 492 }; 493 494 sata: sata@3200000 { 495 compatible = "fsl,ls1088a-ahci"; 496 reg = <0x0 0x3200000 0x0 0x10000>, 497 <0x7 0x100520 0x0 0x4>; 498 reg-names = "ahci", "sata-ecc"; 499 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&clockgen 4 3>; 501 dma-coherent; 502 status = "disabled"; 503 }; 504 505 crypto: crypto@8000000 { 506 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 507 fsl,sec-era = <8>; 508 #address-cells = <1>; 509 #size-cells = <1>; 510 ranges = <0x0 0x00 0x8000000 0x100000>; 511 reg = <0x00 0x8000000 0x0 0x100000>; 512 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 513 dma-coherent; 514 515 sec_jr0: jr@10000 { 516 compatible = "fsl,sec-v5.0-job-ring", 517 "fsl,sec-v4.0-job-ring"; 518 reg = <0x10000 0x10000>; 519 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 520 }; 521 522 sec_jr1: jr@20000 { 523 compatible = "fsl,sec-v5.0-job-ring", 524 "fsl,sec-v4.0-job-ring"; 525 reg = <0x20000 0x10000>; 526 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 527 }; 528 529 sec_jr2: jr@30000 { 530 compatible = "fsl,sec-v5.0-job-ring", 531 "fsl,sec-v4.0-job-ring"; 532 reg = <0x30000 0x10000>; 533 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 534 }; 535 536 sec_jr3: jr@40000 { 537 compatible = "fsl,sec-v5.0-job-ring", 538 "fsl,sec-v4.0-job-ring"; 539 reg = <0x40000 0x10000>; 540 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 541 }; 542 }; 543 544 pcie@3400000 { 545 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; 546 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 547 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 548 reg-names = "regs", "config"; 549 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 550 interrupt-names = "aer"; 551 #address-cells = <3>; 552 #size-cells = <2>; 553 device_type = "pci"; 554 dma-coherent; 555 num-lanes = <4>; 556 bus-range = <0x0 0xff>; 557 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 558 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 559 msi-parent = <&its>; 560 #interrupt-cells = <1>; 561 interrupt-map-mask = <0 0 0 7>; 562 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 563 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 564 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 565 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 566 }; 567 568 pcie@3500000 { 569 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; 570 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 571 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 572 reg-names = "regs", "config"; 573 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 574 interrupt-names = "aer"; 575 #address-cells = <3>; 576 #size-cells = <2>; 577 device_type = "pci"; 578 dma-coherent; 579 num-lanes = <4>; 580 bus-range = <0x0 0xff>; 581 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 582 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 583 msi-parent = <&its>; 584 #interrupt-cells = <1>; 585 interrupt-map-mask = <0 0 0 7>; 586 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 587 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 588 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 589 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 590 }; 591 592 pcie@3600000 { 593 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; 594 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 595 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 596 reg-names = "regs", "config"; 597 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 598 interrupt-names = "aer"; 599 #address-cells = <3>; 600 #size-cells = <2>; 601 device_type = "pci"; 602 dma-coherent; 603 num-lanes = <8>; 604 bus-range = <0x0 0xff>; 605 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 606 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 607 msi-parent = <&its>; 608 #interrupt-cells = <1>; 609 interrupt-map-mask = <0 0 0 7>; 610 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 611 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 612 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 613 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 614 }; 615 }; 616 617 firmware { 618 optee { 619 compatible = "linaro,optee-tz"; 620 method = "smc"; 621 }; 622 }; 623 624}; 625