1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1088A family SoC. 4 * 5 * Copyright 2017-2020 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1088a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 crypto = &crypto; 22 rtc1 = &ftm_alarm0; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 /* We have 2 clusters having 4 Cortex-A53 cores each */ 30 cpu0: cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a53"; 33 reg = <0x0>; 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 35 cpu-idle-states = <&CPU_PH20>; 36 #cooling-cells = <2>; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x1>; 43 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 44 cpu-idle-states = <&CPU_PH20>; 45 #cooling-cells = <2>; 46 }; 47 48 cpu2: cpu@2 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <0x2>; 52 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 53 cpu-idle-states = <&CPU_PH20>; 54 #cooling-cells = <2>; 55 }; 56 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x3>; 61 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 62 cpu-idle-states = <&CPU_PH20>; 63 #cooling-cells = <2>; 64 }; 65 66 cpu4: cpu@100 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x100>; 70 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 71 cpu-idle-states = <&CPU_PH20>; 72 #cooling-cells = <2>; 73 }; 74 75 cpu5: cpu@101 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 reg = <0x101>; 79 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 80 cpu-idle-states = <&CPU_PH20>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu6: cpu@102 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a53"; 87 reg = <0x102>; 88 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 89 cpu-idle-states = <&CPU_PH20>; 90 #cooling-cells = <2>; 91 }; 92 93 cpu7: cpu@103 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x103>; 97 clocks = <&clockgen QORIQ_CLK_CMUX 1>; 98 cpu-idle-states = <&CPU_PH20>; 99 #cooling-cells = <2>; 100 }; 101 102 CPU_PH20: cpu-ph20 { 103 compatible = "arm,idle-state"; 104 idle-state-name = "PH20"; 105 arm,psci-suspend-param = <0x0>; 106 entry-latency-us = <1000>; 107 exit-latency-us = <1000>; 108 min-residency-us = <3000>; 109 }; 110 }; 111 112 gic: interrupt-controller@6000000 { 113 compatible = "arm,gic-v3"; 114 #interrupt-cells = <3>; 115 interrupt-controller; 116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 121 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 its: msi-controller@6020000 { 127 compatible = "arm,gic-v3-its"; 128 msi-controller; 129 #msi-cells = <1>; 130 reg = <0x0 0x6020000 0 0x20000>; 131 }; 132 }; 133 134 thermal-zones { 135 cluster-thermal { 136 polling-delay-passive = <1000>; 137 polling-delay = <5000>; 138 thermal-sensors = <&tmu 0>; 139 140 trips { 141 core_cluster_alert: core-cluster-alert { 142 temperature = <85000>; 143 hysteresis = <2000>; 144 type = "passive"; 145 }; 146 147 core-cluster-crit { 148 temperature = <95000>; 149 hysteresis = <2000>; 150 type = "critical"; 151 }; 152 }; 153 154 cooling-maps { 155 map0 { 156 trip = <&core_cluster_alert>; 157 cooling-device = 158 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 159 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 160 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 161 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 162 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 163 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 164 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 165 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 166 }; 167 }; 168 }; 169 170 soc-thermal { 171 polling-delay-passive = <1000>; 172 polling-delay = <5000>; 173 thermal-sensors = <&tmu 1>; 174 175 trips { 176 soc-crit { 177 temperature = <95000>; 178 hysteresis = <2000>; 179 type = "critical"; 180 }; 181 }; 182 }; 183 }; 184 185 timer { 186 compatible = "arm,armv8-timer"; 187 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 188 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 189 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 190 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 191 }; 192 193 pmu { 194 compatible = "arm,cortex-a53-pmu"; 195 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 196 }; 197 198 psci { 199 compatible = "arm,psci-0.2"; 200 method = "smc"; 201 }; 202 203 sysclk: sysclk { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <100000000>; 207 clock-output-names = "sysclk"; 208 }; 209 210 reboot { 211 compatible = "syscon-reboot"; 212 regmap = <&reset>; 213 offset = <0x0>; 214 mask = <0x02>; 215 }; 216 217 soc { 218 compatible = "simple-bus"; 219 #address-cells = <2>; 220 #size-cells = <2>; 221 ranges; 222 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 223 224 clockgen: clocking@1300000 { 225 compatible = "fsl,ls1088a-clockgen"; 226 reg = <0 0x1300000 0 0xa0000>; 227 #clock-cells = <2>; 228 clocks = <&sysclk>; 229 }; 230 231 dcfg: dcfg@1e00000 { 232 compatible = "fsl,ls1088a-dcfg", "syscon"; 233 reg = <0x0 0x1e00000 0x0 0x10000>; 234 little-endian; 235 }; 236 237 reset: syscon@1e60000 { 238 compatible = "fsl,ls1088a-reset", "syscon"; 239 reg = <0x0 0x1e60000 0x0 0x10000>; 240 }; 241 242 isc: syscon@1f70000 { 243 compatible = "fsl,ls1088a-isc", "syscon"; 244 reg = <0x0 0x1f70000 0x0 0x10000>; 245 little-endian; 246 #address-cells = <1>; 247 #size-cells = <1>; 248 ranges = <0x0 0x0 0x1f70000 0x10000>; 249 250 extirq: interrupt-controller@14 { 251 compatible = "fsl,ls1088a-extirq"; 252 #interrupt-cells = <2>; 253 #address-cells = <0>; 254 interrupt-controller; 255 reg = <0x14 4>; 256 interrupt-map = 257 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 258 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 259 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 260 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 261 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 262 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 263 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 264 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 265 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 266 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 267 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 268 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 269 interrupt-map-mask = <0xf 0x0>; 270 }; 271 }; 272 273 sfp: efuse@1e80000 { 274 compatible = "fsl,ls1028a-sfp"; 275 reg = <0x0 0x1e80000 0x0 0x10000>; 276 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 277 QORIQ_CLK_PLL_DIV(4)>; 278 clock-names = "sfp"; 279 }; 280 281 tmu: tmu@1f80000 { 282 compatible = "fsl,qoriq-tmu"; 283 reg = <0x0 0x1f80000 0x0 0x10000>; 284 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 285 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 286 fsl,tmu-calibration = 287 /* Calibration data group 1 */ 288 <0x00000000 0x00000023>, 289 <0x00000001 0x0000002a>, 290 <0x00000002 0x00000030>, 291 <0x00000003 0x00000037>, 292 <0x00000004 0x0000003d>, 293 <0x00000005 0x00000044>, 294 <0x00000006 0x0000004a>, 295 <0x00000007 0x00000051>, 296 <0x00000008 0x00000057>, 297 <0x00000009 0x0000005e>, 298 <0x0000000a 0x00000064>, 299 <0x0000000b 0x0000006b>, 300 /* Calibration data group 2 */ 301 <0x00010000 0x00000022>, 302 <0x00010001 0x0000002a>, 303 <0x00010002 0x00000032>, 304 <0x00010003 0x0000003a>, 305 <0x00010004 0x00000042>, 306 <0x00010005 0x0000004a>, 307 <0x00010006 0x00000052>, 308 <0x00010007 0x0000005a>, 309 <0x00010008 0x00000062>, 310 <0x00010009 0x0000006a>, 311 /* Calibration data group 3 */ 312 <0x00020000 0x00000021>, 313 <0x00020001 0x0000002b>, 314 <0x00020002 0x00000035>, 315 <0x00020003 0x00000040>, 316 <0x00020004 0x0000004a>, 317 <0x00020005 0x00000054>, 318 <0x00020006 0x0000005e>, 319 /* Calibration data group 4 */ 320 <0x00030000 0x00000010>, 321 <0x00030001 0x0000001c>, 322 <0x00030002 0x00000027>, 323 <0x00030003 0x00000032>, 324 <0x00030004 0x0000003e>, 325 <0x00030005 0x00000049>, 326 <0x00030006 0x00000054>, 327 <0x00030007 0x00000060>; 328 little-endian; 329 #thermal-sensor-cells = <1>; 330 }; 331 332 dspi: spi@2100000 { 333 compatible = "fsl,ls1088a-dspi", 334 "fsl,ls1021a-v1.0-dspi"; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 reg = <0x0 0x2100000 0x0 0x10000>; 338 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 339 clock-names = "dspi"; 340 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 341 QORIQ_CLK_PLL_DIV(2)>; 342 spi-num-chipselects = <6>; 343 status = "disabled"; 344 }; 345 346 duart0: serial@21c0500 { 347 compatible = "fsl,ns16550", "ns16550a"; 348 reg = <0x0 0x21c0500 0x0 0x100>; 349 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 350 QORIQ_CLK_PLL_DIV(4)>; 351 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 352 status = "disabled"; 353 }; 354 355 duart1: serial@21c0600 { 356 compatible = "fsl,ns16550", "ns16550a"; 357 reg = <0x0 0x21c0600 0x0 0x100>; 358 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 359 QORIQ_CLK_PLL_DIV(4)>; 360 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 361 status = "disabled"; 362 }; 363 364 gpio0: gpio@2300000 { 365 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 366 reg = <0x0 0x2300000 0x0 0x10000>; 367 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 368 little-endian; 369 gpio-controller; 370 #gpio-cells = <2>; 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 }; 374 375 gpio1: gpio@2310000 { 376 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 377 reg = <0x0 0x2310000 0x0 0x10000>; 378 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 379 little-endian; 380 gpio-controller; 381 #gpio-cells = <2>; 382 interrupt-controller; 383 #interrupt-cells = <2>; 384 }; 385 386 gpio2: gpio@2320000 { 387 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 388 reg = <0x0 0x2320000 0x0 0x10000>; 389 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 390 little-endian; 391 gpio-controller; 392 #gpio-cells = <2>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 }; 396 397 gpio3: gpio@2330000 { 398 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 399 reg = <0x0 0x2330000 0x0 0x10000>; 400 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 401 little-endian; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 }; 407 408 ifc: memory-controller@2240000 { 409 compatible = "fsl,ifc"; 410 reg = <0x0 0x2240000 0x0 0x20000>; 411 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 412 little-endian; 413 #address-cells = <2>; 414 #size-cells = <1>; 415 status = "disabled"; 416 }; 417 418 i2c0: i2c@2000000 { 419 compatible = "fsl,vf610-i2c"; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 reg = <0x0 0x2000000 0x0 0x10000>; 423 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 425 QORIQ_CLK_PLL_DIV(8)>; 426 status = "disabled"; 427 }; 428 429 i2c1: i2c@2010000 { 430 compatible = "fsl,vf610-i2c"; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 reg = <0x0 0x2010000 0x0 0x10000>; 434 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 436 QORIQ_CLK_PLL_DIV(8)>; 437 status = "disabled"; 438 }; 439 440 i2c2: i2c@2020000 { 441 compatible = "fsl,vf610-i2c"; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 reg = <0x0 0x2020000 0x0 0x10000>; 445 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 447 QORIQ_CLK_PLL_DIV(8)>; 448 status = "disabled"; 449 }; 450 451 i2c3: i2c@2030000 { 452 compatible = "fsl,vf610-i2c"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 reg = <0x0 0x2030000 0x0 0x10000>; 456 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 458 QORIQ_CLK_PLL_DIV(8)>; 459 status = "disabled"; 460 }; 461 462 qspi: spi@20c0000 { 463 compatible = "fsl,ls2080a-qspi"; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 reg = <0x0 0x20c0000 0x0 0x10000>, 467 <0x0 0x20000000 0x0 0x10000000>; 468 reg-names = "QuadSPI", "QuadSPI-memory"; 469 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 470 clock-names = "qspi_en", "qspi"; 471 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 472 QORIQ_CLK_PLL_DIV(4)>, 473 <&clockgen QORIQ_CLK_PLATFORM_PLL 474 QORIQ_CLK_PLL_DIV(4)>; 475 status = "disabled"; 476 }; 477 478 esdhc: mmc@2140000 { 479 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 480 reg = <0x0 0x2140000 0x0 0x10000>; 481 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 482 clock-frequency = <0>; 483 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 484 voltage-ranges = <1800 1800 3300 3300>; 485 sdhci,auto-cmd12; 486 little-endian; 487 bus-width = <4>; 488 status = "disabled"; 489 }; 490 491 usb0: usb@3100000 { 492 compatible = "snps,dwc3"; 493 reg = <0x0 0x3100000 0x0 0x10000>; 494 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 495 dr_mode = "host"; 496 snps,quirk-frame-length-adjustment = <0x20>; 497 snps,dis_rxdet_inp3_quirk; 498 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 499 status = "disabled"; 500 }; 501 502 usb1: usb@3110000 { 503 compatible = "snps,dwc3"; 504 reg = <0x0 0x3110000 0x0 0x10000>; 505 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 506 dr_mode = "host"; 507 snps,quirk-frame-length-adjustment = <0x20>; 508 snps,dis_rxdet_inp3_quirk; 509 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 510 status = "disabled"; 511 }; 512 513 sata: sata@3200000 { 514 compatible = "fsl,ls1088a-ahci"; 515 reg = <0x0 0x3200000 0x0 0x10000>, 516 <0x7 0x100520 0x0 0x4>; 517 reg-names = "ahci", "sata-ecc"; 518 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 520 QORIQ_CLK_PLL_DIV(4)>; 521 dma-coherent; 522 status = "disabled"; 523 }; 524 525 crypto: crypto@8000000 { 526 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 527 fsl,sec-era = <8>; 528 #address-cells = <1>; 529 #size-cells = <1>; 530 ranges = <0x0 0x00 0x8000000 0x100000>; 531 reg = <0x00 0x8000000 0x0 0x100000>; 532 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 533 dma-coherent; 534 535 sec_jr0: jr@10000 { 536 compatible = "fsl,sec-v5.0-job-ring", 537 "fsl,sec-v4.0-job-ring"; 538 reg = <0x10000 0x10000>; 539 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 540 }; 541 542 sec_jr1: jr@20000 { 543 compatible = "fsl,sec-v5.0-job-ring", 544 "fsl,sec-v4.0-job-ring"; 545 reg = <0x20000 0x10000>; 546 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 547 }; 548 549 sec_jr2: jr@30000 { 550 compatible = "fsl,sec-v5.0-job-ring", 551 "fsl,sec-v4.0-job-ring"; 552 reg = <0x30000 0x10000>; 553 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 554 }; 555 556 sec_jr3: jr@40000 { 557 compatible = "fsl,sec-v5.0-job-ring", 558 "fsl,sec-v4.0-job-ring"; 559 reg = <0x40000 0x10000>; 560 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 561 }; 562 }; 563 564 pcie1: pcie@3400000 { 565 compatible = "fsl,ls1088a-pcie"; 566 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 567 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 568 reg-names = "regs", "config"; 569 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 570 interrupt-names = "aer"; 571 #address-cells = <3>; 572 #size-cells = <2>; 573 device_type = "pci"; 574 dma-coherent; 575 num-viewport = <256>; 576 bus-range = <0x0 0xff>; 577 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 578 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 579 msi-parent = <&its 0>; 580 #interrupt-cells = <1>; 581 interrupt-map-mask = <0 0 0 7>; 582 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 583 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 584 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 585 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 586 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 587 status = "disabled"; 588 }; 589 590 pcie_ep1: pcie-ep@3400000 { 591 compatible = "fsl,ls1088a-pcie-ep"; 592 reg = <0x00 0x03400000 0x0 0x00100000>, 593 <0x20 0x00000000 0x8 0x00000000>; 594 reg-names = "regs", "addr_space"; 595 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 596 interrupt-names = "pme"; 597 num-ib-windows = <24>; 598 num-ob-windows = <256>; 599 max-functions = /bits/ 8 <2>; 600 status = "disabled"; 601 }; 602 603 pcie2: pcie@3500000 { 604 compatible = "fsl,ls1088a-pcie"; 605 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 606 <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 607 reg-names = "regs", "config"; 608 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 609 interrupt-names = "aer"; 610 #address-cells = <3>; 611 #size-cells = <2>; 612 device_type = "pci"; 613 dma-coherent; 614 num-viewport = <6>; 615 bus-range = <0x0 0xff>; 616 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 617 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 618 msi-parent = <&its 0>; 619 #interrupt-cells = <1>; 620 interrupt-map-mask = <0 0 0 7>; 621 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 622 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 623 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 624 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 625 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 626 status = "disabled"; 627 }; 628 629 pcie_ep2: pcie-ep@3500000 { 630 compatible = "fsl,ls1088a-pcie-ep"; 631 reg = <0x00 0x03500000 0x0 0x00100000>, 632 <0x28 0x00000000 0x8 0x00000000>; 633 reg-names = "regs", "addr_space"; 634 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 635 interrupt-names = "pme"; 636 num-ib-windows = <6>; 637 num-ob-windows = <6>; 638 status = "disabled"; 639 }; 640 641 pcie3: pcie@3600000 { 642 compatible = "fsl,ls1088a-pcie"; 643 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 644 <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 645 reg-names = "regs", "config"; 646 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 647 interrupt-names = "aer"; 648 #address-cells = <3>; 649 #size-cells = <2>; 650 device_type = "pci"; 651 dma-coherent; 652 num-viewport = <6>; 653 bus-range = <0x0 0xff>; 654 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 655 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 656 msi-parent = <&its 0>; 657 #interrupt-cells = <1>; 658 interrupt-map-mask = <0 0 0 7>; 659 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 660 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 661 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 662 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 663 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 664 status = "disabled"; 665 }; 666 667 pcie_ep3: pcie-ep@3600000 { 668 compatible = "fsl,ls1088a-pcie-ep"; 669 reg = <0x00 0x03600000 0x0 0x00100000>, 670 <0x30 0x00000000 0x8 0x00000000>; 671 reg-names = "regs", "addr_space"; 672 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 673 interrupt-names = "pme"; 674 num-ib-windows = <6>; 675 num-ob-windows = <6>; 676 status = "disabled"; 677 }; 678 679 smmu: iommu@5000000 { 680 compatible = "arm,mmu-500"; 681 reg = <0 0x5000000 0 0x800000>; 682 #iommu-cells = <1>; 683 stream-match-mask = <0x7C00>; 684 dma-coherent; 685 #global-interrupts = <12>; 686 // global secure fault 687 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 688 // combined secure 689 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 690 // global non-secure fault 691 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 692 // combined non-secure 693 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 694 // performance counter interrupts 0-7 695 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 703 // per context interrupt, 64 interrupts 704 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 768 }; 769 770 console@8340020 { 771 compatible = "fsl,dpaa2-console"; 772 reg = <0x00000000 0x08340020 0 0x2>; 773 }; 774 775 ptp-timer@8b95000 { 776 compatible = "fsl,dpaa2-ptp"; 777 reg = <0x0 0x8b95000 0x0 0x100>; 778 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 779 QORIQ_CLK_PLL_DIV(1)>; 780 little-endian; 781 fsl,extts-fifo; 782 }; 783 784 emdio1: mdio@8b96000 { 785 compatible = "fsl,fman-memac-mdio"; 786 reg = <0x0 0x8b96000 0x0 0x1000>; 787 little-endian; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 clock-frequency = <2500000>; 791 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 792 QORIQ_CLK_PLL_DIV(1)>; 793 status = "disabled"; 794 }; 795 796 emdio2: mdio@8b97000 { 797 compatible = "fsl,fman-memac-mdio"; 798 reg = <0x0 0x8b97000 0x0 0x1000>; 799 little-endian; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 clock-frequency = <2500000>; 803 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 804 QORIQ_CLK_PLL_DIV(1)>; 805 status = "disabled"; 806 }; 807 808 pcs_mdio1: mdio@8c07000 { 809 compatible = "fsl,fman-memac-mdio"; 810 reg = <0x0 0x8c07000 0x0 0x1000>; 811 little-endian; 812 #address-cells = <1>; 813 #size-cells = <0>; 814 status = "disabled"; 815 816 pcs1: ethernet-phy@0 { 817 reg = <0>; 818 }; 819 }; 820 821 pcs_mdio2: mdio@8c0b000 { 822 compatible = "fsl,fman-memac-mdio"; 823 reg = <0x0 0x8c0b000 0x0 0x1000>; 824 little-endian; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 status = "disabled"; 828 829 pcs2: ethernet-phy@0 { 830 reg = <0>; 831 }; 832 }; 833 834 pcs_mdio3: mdio@8c0f000 { 835 compatible = "fsl,fman-memac-mdio"; 836 reg = <0x0 0x8c0f000 0x0 0x1000>; 837 little-endian; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 status = "disabled"; 841 842 pcs3_0: ethernet-phy@0 { 843 reg = <0>; 844 }; 845 846 pcs3_1: ethernet-phy@1 { 847 reg = <1>; 848 }; 849 850 pcs3_2: ethernet-phy@2 { 851 reg = <2>; 852 }; 853 854 pcs3_3: ethernet-phy@3 { 855 reg = <3>; 856 }; 857 }; 858 859 pcs_mdio7: mdio@8c1f000 { 860 compatible = "fsl,fman-memac-mdio"; 861 reg = <0x0 0x8c1f000 0x0 0x1000>; 862 little-endian; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 status = "disabled"; 866 867 pcs7_0: ethernet-phy@0 { 868 reg = <0>; 869 }; 870 871 pcs7_1: ethernet-phy@1 { 872 reg = <1>; 873 }; 874 875 pcs7_2: ethernet-phy@2 { 876 reg = <2>; 877 }; 878 879 pcs7_3: ethernet-phy@3 { 880 reg = <3>; 881 }; 882 }; 883 884 cluster1_core0_watchdog: watchdog@c000000 { 885 compatible = "arm,sp805", "arm,primecell"; 886 reg = <0x0 0xc000000 0x0 0x1000>; 887 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 888 QORIQ_CLK_PLL_DIV(16)>, 889 <&clockgen QORIQ_CLK_PLATFORM_PLL 890 QORIQ_CLK_PLL_DIV(16)>; 891 clock-names = "wdog_clk", "apb_pclk"; 892 }; 893 894 cluster1_core1_watchdog: watchdog@c010000 { 895 compatible = "arm,sp805", "arm,primecell"; 896 reg = <0x0 0xc010000 0x0 0x1000>; 897 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 898 QORIQ_CLK_PLL_DIV(16)>, 899 <&clockgen QORIQ_CLK_PLATFORM_PLL 900 QORIQ_CLK_PLL_DIV(16)>; 901 clock-names = "wdog_clk", "apb_pclk"; 902 }; 903 904 cluster1_core2_watchdog: watchdog@c020000 { 905 compatible = "arm,sp805", "arm,primecell"; 906 reg = <0x0 0xc020000 0x0 0x1000>; 907 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 908 QORIQ_CLK_PLL_DIV(16)>, 909 <&clockgen QORIQ_CLK_PLATFORM_PLL 910 QORIQ_CLK_PLL_DIV(16)>; 911 clock-names = "wdog_clk", "apb_pclk"; 912 }; 913 914 cluster1_core3_watchdog: watchdog@c030000 { 915 compatible = "arm,sp805", "arm,primecell"; 916 reg = <0x0 0xc030000 0x0 0x1000>; 917 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 918 QORIQ_CLK_PLL_DIV(16)>, 919 <&clockgen QORIQ_CLK_PLATFORM_PLL 920 QORIQ_CLK_PLL_DIV(16)>; 921 clock-names = "wdog_clk", "apb_pclk"; 922 }; 923 924 cluster2_core0_watchdog: watchdog@c100000 { 925 compatible = "arm,sp805", "arm,primecell"; 926 reg = <0x0 0xc100000 0x0 0x1000>; 927 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 928 QORIQ_CLK_PLL_DIV(16)>, 929 <&clockgen QORIQ_CLK_PLATFORM_PLL 930 QORIQ_CLK_PLL_DIV(16)>; 931 clock-names = "wdog_clk", "apb_pclk"; 932 }; 933 934 cluster2_core1_watchdog: watchdog@c110000 { 935 compatible = "arm,sp805", "arm,primecell"; 936 reg = <0x0 0xc110000 0x0 0x1000>; 937 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 938 QORIQ_CLK_PLL_DIV(16)>, 939 <&clockgen QORIQ_CLK_PLATFORM_PLL 940 QORIQ_CLK_PLL_DIV(16)>; 941 clock-names = "wdog_clk", "apb_pclk"; 942 }; 943 944 cluster2_core2_watchdog: watchdog@c120000 { 945 compatible = "arm,sp805", "arm,primecell"; 946 reg = <0x0 0xc120000 0x0 0x1000>; 947 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 948 QORIQ_CLK_PLL_DIV(16)>, 949 <&clockgen QORIQ_CLK_PLATFORM_PLL 950 QORIQ_CLK_PLL_DIV(16)>; 951 clock-names = "wdog_clk", "apb_pclk"; 952 }; 953 954 cluster2_core3_watchdog: watchdog@c130000 { 955 compatible = "arm,sp805", "arm,primecell"; 956 reg = <0x0 0xc130000 0x0 0x1000>; 957 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 958 QORIQ_CLK_PLL_DIV(16)>, 959 <&clockgen QORIQ_CLK_PLATFORM_PLL 960 QORIQ_CLK_PLL_DIV(16)>; 961 clock-names = "wdog_clk", "apb_pclk"; 962 }; 963 964 fsl_mc: fsl-mc@80c000000 { 965 compatible = "fsl,qoriq-mc"; 966 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 967 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 968 msi-parent = <&its 0>; 969 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 970 dma-coherent; 971 #address-cells = <3>; 972 #size-cells = <1>; 973 974 /* 975 * Region type 0x0 - MC portals 976 * Region type 0x1 - QBMAN portals 977 */ 978 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 979 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 980 981 dpmacs { 982 #address-cells = <1>; 983 #size-cells = <0>; 984 985 dpmac1: ethernet@1 { 986 compatible = "fsl,qoriq-mc-dpmac"; 987 reg = <1>; 988 }; 989 990 dpmac2: ethernet@2 { 991 compatible = "fsl,qoriq-mc-dpmac"; 992 reg = <2>; 993 }; 994 995 dpmac3: ethernet@3 { 996 compatible = "fsl,qoriq-mc-dpmac"; 997 reg = <3>; 998 }; 999 1000 dpmac4: ethernet@4 { 1001 compatible = "fsl,qoriq-mc-dpmac"; 1002 reg = <4>; 1003 }; 1004 1005 dpmac5: ethernet@5 { 1006 compatible = "fsl,qoriq-mc-dpmac"; 1007 reg = <5>; 1008 }; 1009 1010 dpmac6: ethernet@6 { 1011 compatible = "fsl,qoriq-mc-dpmac"; 1012 reg = <6>; 1013 }; 1014 1015 dpmac7: ethernet@7 { 1016 compatible = "fsl,qoriq-mc-dpmac"; 1017 reg = <7>; 1018 }; 1019 1020 dpmac8: ethernet@8 { 1021 compatible = "fsl,qoriq-mc-dpmac"; 1022 reg = <8>; 1023 }; 1024 1025 dpmac9: ethernet@9 { 1026 compatible = "fsl,qoriq-mc-dpmac"; 1027 reg = <9>; 1028 }; 1029 1030 dpmac10: ethernet@a { 1031 compatible = "fsl,qoriq-mc-dpmac"; 1032 reg = <0xa>; 1033 }; 1034 }; 1035 }; 1036 1037 rcpm: wakeup-controller@1e34040 { 1038 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1039 reg = <0x0 0x1e34040 0x0 0x18>; 1040 #fsl,rcpm-wakeup-cells = <6>; 1041 little-endian; 1042 }; 1043 1044 ftm_alarm0: rtc@2800000 { 1045 compatible = "fsl,ls1088a-ftm-alarm"; 1046 reg = <0x0 0x2800000 0x0 0x10000>; 1047 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; 1048 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1049 }; 1050 }; 1051 1052 firmware { 1053 optee { 1054 compatible = "linaro,optee-tz"; 1055 method = "smc"; 1056 }; 1057 }; 1058}; 1059