1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 4 * 5 * Copyright 2016 Freescale Semiconductor, Inc. 6 * Copyright 2018, 2020 NXP 7 * 8 * Mingkai Hu <mingkai.hu@nxp.com> 9 */ 10 11#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/gpio/gpio.h> 15 16/ { 17 compatible = "fsl,ls1046a"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 crypto = &crypto; 24 fman0 = &fman0; 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 ethernet4 = &enet4; 30 ethernet5 = &enet5; 31 ethernet6 = &enet6; 32 ethernet7 = &enet7; 33 rtc1 = &ftm_alarm0; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a72"; 43 reg = <0x0>; 44 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 45 next-level-cache = <&l2>; 46 cpu-idle-states = <&CPU_PH20>; 47 #cooling-cells = <2>; 48 }; 49 50 cpu1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a72"; 53 reg = <0x1>; 54 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 55 next-level-cache = <&l2>; 56 cpu-idle-states = <&CPU_PH20>; 57 #cooling-cells = <2>; 58 }; 59 60 cpu2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a72"; 63 reg = <0x2>; 64 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 65 next-level-cache = <&l2>; 66 cpu-idle-states = <&CPU_PH20>; 67 #cooling-cells = <2>; 68 }; 69 70 cpu3: cpu@3 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a72"; 73 reg = <0x3>; 74 clocks = <&clockgen QORIQ_CLK_CMUX 0>; 75 next-level-cache = <&l2>; 76 cpu-idle-states = <&CPU_PH20>; 77 #cooling-cells = <2>; 78 }; 79 80 l2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 }; 85 }; 86 87 idle-states { 88 /* 89 * PSCI node is not added default, U-boot will add missing 90 * parts if it determines to use PSCI. 91 */ 92 entry-method = "psci"; 93 94 CPU_PH20: cpu-ph20 { 95 compatible = "arm,idle-state"; 96 idle-state-name = "PH20"; 97 arm,psci-suspend-param = <0x0>; 98 entry-latency-us = <1000>; 99 exit-latency-us = <1000>; 100 min-residency-us = <3000>; 101 }; 102 }; 103 104 memory@80000000 { 105 device_type = "memory"; 106 /* Real size will be filled by bootloader */ 107 reg = <0x0 0x80000000 0x0 0x0>; 108 }; 109 110 sysclk: sysclk { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <100000000>; 114 clock-output-names = "sysclk"; 115 }; 116 117 reboot { 118 compatible = "syscon-reboot"; 119 regmap = <&dcfg>; 120 offset = <0xb0>; 121 mask = <0x02>; 122 }; 123 124 thermal-zones { 125 ddr-thermal { 126 polling-delay-passive = <1000>; 127 polling-delay = <5000>; 128 thermal-sensors = <&tmu 0>; 129 130 trips { 131 ddr-ctrler-alert { 132 temperature = <85000>; 133 hysteresis = <2000>; 134 type = "passive"; 135 }; 136 137 ddr-ctrler-crit { 138 temperature = <95000>; 139 hysteresis = <2000>; 140 type = "critical"; 141 }; 142 }; 143 }; 144 145 serdes-thermal { 146 polling-delay-passive = <1000>; 147 polling-delay = <5000>; 148 thermal-sensors = <&tmu 1>; 149 150 trips { 151 serdes-alert { 152 temperature = <85000>; 153 hysteresis = <2000>; 154 type = "passive"; 155 }; 156 157 serdes-crit { 158 temperature = <95000>; 159 hysteresis = <2000>; 160 type = "critical"; 161 }; 162 }; 163 }; 164 165 fman-thermal { 166 polling-delay-passive = <1000>; 167 polling-delay = <5000>; 168 thermal-sensors = <&tmu 2>; 169 170 trips { 171 fman-alert { 172 temperature = <85000>; 173 hysteresis = <2000>; 174 type = "passive"; 175 }; 176 177 fman-crit { 178 temperature = <95000>; 179 hysteresis = <2000>; 180 type = "critical"; 181 }; 182 }; 183 }; 184 185 cluster-thermal { 186 polling-delay-passive = <1000>; 187 polling-delay = <5000>; 188 thermal-sensors = <&tmu 3>; 189 190 trips { 191 core_cluster_alert: core-cluster-alert { 192 temperature = <85000>; 193 hysteresis = <2000>; 194 type = "passive"; 195 }; 196 197 core_cluster_crit: core-cluster-crit { 198 temperature = <95000>; 199 hysteresis = <2000>; 200 type = "critical"; 201 }; 202 }; 203 204 cooling-maps { 205 map0 { 206 trip = <&core_cluster_alert>; 207 cooling-device = 208 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 212 }; 213 }; 214 }; 215 216 sec-thermal { 217 polling-delay-passive = <1000>; 218 polling-delay = <5000>; 219 thermal-sensors = <&tmu 4>; 220 221 trips { 222 sec-alert { 223 temperature = <85000>; 224 hysteresis = <2000>; 225 type = "passive"; 226 }; 227 228 sec-crit { 229 temperature = <95000>; 230 hysteresis = <2000>; 231 type = "critical"; 232 }; 233 }; 234 }; 235 }; 236 237 timer { 238 compatible = "arm,armv8-timer"; 239 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | 240 IRQ_TYPE_LEVEL_LOW)>, 241 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | 242 IRQ_TYPE_LEVEL_LOW)>, 243 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | 244 IRQ_TYPE_LEVEL_LOW)>, 245 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | 246 IRQ_TYPE_LEVEL_LOW)>; 247 }; 248 249 pmu { 250 compatible = "arm,cortex-a72-pmu"; 251 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 255 interrupt-affinity = <&cpu0>, 256 <&cpu1>, 257 <&cpu2>, 258 <&cpu3>; 259 }; 260 261 gic: interrupt-controller@1400000 { 262 compatible = "arm,gic-400"; 263 #interrupt-cells = <3>; 264 interrupt-controller; 265 reg = <0x0 0x1410000 0 0x10000>, /* GICD */ 266 <0x0 0x1420000 0 0x20000>, /* GICC */ 267 <0x0 0x1440000 0 0x20000>, /* GICH */ 268 <0x0 0x1460000 0 0x20000>; /* GICV */ 269 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 270 IRQ_TYPE_LEVEL_LOW)>; 271 }; 272 273 soc: soc { 274 compatible = "simple-bus"; 275 #address-cells = <2>; 276 #size-cells = <2>; 277 ranges; 278 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 279 dma-coherent; 280 281 ddr: memory-controller@1080000 { 282 compatible = "fsl,qoriq-memory-controller"; 283 reg = <0x0 0x1080000 0x0 0x1000>; 284 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 285 }; 286 287 ifc: memory-controller@1530000 { 288 compatible = "fsl,ifc"; 289 reg = <0x0 0x1530000 0x0 0x10000>; 290 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 291 status = "disabled"; 292 }; 293 294 qspi: spi@1550000 { 295 compatible = "fsl,ls1021a-qspi"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <0x0 0x1550000 0x0 0x10000>, 299 <0x0 0x40000000 0x0 0x10000000>; 300 reg-names = "QuadSPI", "QuadSPI-memory"; 301 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 302 clock-names = "qspi_en", "qspi"; 303 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 304 QORIQ_CLK_PLL_DIV(2)>, 305 <&clockgen QORIQ_CLK_PLATFORM_PLL 306 QORIQ_CLK_PLL_DIV(2)>; 307 status = "disabled"; 308 }; 309 310 esdhc: mmc@1560000 { 311 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 312 reg = <0x0 0x1560000 0x0 0x10000>; 313 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 315 voltage-ranges = <1800 1800 3300 3300>; 316 sdhci,auto-cmd12; 317 bus-width = <4>; 318 }; 319 320 scfg: scfg@1570000 { 321 compatible = "fsl,ls1046a-scfg", "syscon"; 322 reg = <0x0 0x1570000 0x0 0x10000>; 323 big-endian; 324 #address-cells = <1>; 325 #size-cells = <1>; 326 ranges = <0x0 0x0 0x1570000 0x10000>; 327 328 extirq: interrupt-controller@1ac { 329 compatible = "fsl,ls1046a-extirq", "fsl,ls1043a-extirq"; 330 #interrupt-cells = <2>; 331 #address-cells = <0>; 332 interrupt-controller; 333 reg = <0x1ac 4>; 334 interrupt-map = 335 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 336 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 337 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 338 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 339 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 340 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 341 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 342 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 343 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 344 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 345 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 346 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 347 interrupt-map-mask = <0xf 0x0>; 348 }; 349 }; 350 351 crypto: crypto@1700000 { 352 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", 353 "fsl,sec-v4.0"; 354 fsl,sec-era = <8>; 355 #address-cells = <1>; 356 #size-cells = <1>; 357 ranges = <0x0 0x00 0x1700000 0x100000>; 358 reg = <0x00 0x1700000 0x0 0x100000>; 359 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 360 361 sec_jr0: jr@10000 { 362 compatible = "fsl,sec-v5.4-job-ring", 363 "fsl,sec-v5.0-job-ring", 364 "fsl,sec-v4.0-job-ring"; 365 reg = <0x10000 0x10000>; 366 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 367 }; 368 369 sec_jr1: jr@20000 { 370 compatible = "fsl,sec-v5.4-job-ring", 371 "fsl,sec-v5.0-job-ring", 372 "fsl,sec-v4.0-job-ring"; 373 reg = <0x20000 0x10000>; 374 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 375 }; 376 377 sec_jr2: jr@30000 { 378 compatible = "fsl,sec-v5.4-job-ring", 379 "fsl,sec-v5.0-job-ring", 380 "fsl,sec-v4.0-job-ring"; 381 reg = <0x30000 0x10000>; 382 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 383 }; 384 385 sec_jr3: jr@40000 { 386 compatible = "fsl,sec-v5.4-job-ring", 387 "fsl,sec-v5.0-job-ring", 388 "fsl,sec-v4.0-job-ring"; 389 reg = <0x40000 0x10000>; 390 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 391 }; 392 }; 393 394 qman: qman@1880000 { 395 compatible = "fsl,qman"; 396 reg = <0x0 0x1880000 0x0 0x10000>; 397 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 398 memory-region = <&qman_fqd &qman_pfdr>; 399 400 }; 401 402 bman: bman@1890000 { 403 compatible = "fsl,bman"; 404 reg = <0x0 0x1890000 0x0 0x10000>; 405 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 406 memory-region = <&bman_fbpr>; 407 408 }; 409 410 qportals: qman-portals-bus@500000000 { 411 ranges = <0x0 0x5 0x00000000 0x8000000>; 412 }; 413 414 bportals: bman-portals-bus@508000000 { 415 ranges = <0x0 0x5 0x08000000 0x8000000>; 416 }; 417 418 sfp: efuse@1e80000 { 419 compatible = "fsl,ls1021a-sfp"; 420 reg = <0x0 0x1e80000 0x0 0x10000>; 421 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 422 QORIQ_CLK_PLL_DIV(4)>; 423 clock-names = "sfp"; 424 }; 425 426 dcfg: dcfg@1ee0000 { 427 compatible = "fsl,ls1046a-dcfg", "syscon"; 428 reg = <0x0 0x1ee0000 0x0 0x1000>; 429 big-endian; 430 }; 431 432 clockgen: clocking@1ee1000 { 433 compatible = "fsl,ls1046a-clockgen"; 434 reg = <0x0 0x1ee1000 0x0 0x1000>; 435 #clock-cells = <2>; 436 clocks = <&sysclk>; 437 }; 438 439 tmu: tmu@1f00000 { 440 compatible = "fsl,qoriq-tmu"; 441 reg = <0x0 0x1f00000 0x0 0x10000>; 442 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 443 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 444 fsl,tmu-calibration = 445 /* Calibration data group 1 */ 446 <0x00000000 0x00000023>, 447 <0x00000001 0x00000029>, 448 <0x00000002 0x0000002f>, 449 <0x00000003 0x00000036>, 450 <0x00000004 0x0000003c>, 451 <0x00000005 0x00000042>, 452 <0x00000006 0x00000049>, 453 <0x00000007 0x0000004f>, 454 <0x00000008 0x00000055>, 455 <0x00000009 0x0000005c>, 456 <0x0000000a 0x00000062>, 457 <0x0000000b 0x00000068>, 458 /* Calibration data group 2 */ 459 <0x00010000 0x00000022>, 460 <0x00010001 0x0000002a>, 461 <0x00010002 0x00000032>, 462 <0x00010003 0x0000003a>, 463 <0x00010004 0x00000042>, 464 <0x00010005 0x0000004a>, 465 <0x00010006 0x00000052>, 466 <0x00010007 0x0000005a>, 467 <0x00010008 0x00000062>, 468 <0x00010009 0x0000006a>, 469 /* Calibration data group 3 */ 470 <0x00020000 0x00000021>, 471 <0x00020001 0x0000002b>, 472 <0x00020002 0x00000035>, 473 <0x00020003 0x0000003e>, 474 <0x00020004 0x00000048>, 475 <0x00020005 0x00000052>, 476 <0x00020006 0x0000005c>, 477 /* Calibration data group 4 */ 478 <0x00030000 0x00000011>, 479 <0x00030001 0x0000001a>, 480 <0x00030002 0x00000024>, 481 <0x00030003 0x0000002e>, 482 <0x00030004 0x00000038>, 483 <0x00030005 0x00000042>, 484 <0x00030006 0x0000004c>, 485 <0x00030007 0x00000056>; 486 #thermal-sensor-cells = <1>; 487 }; 488 489 dspi: spi@2100000 { 490 compatible = "fsl,ls1021a-v1.0-dspi"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <0x0 0x2100000 0x0 0x10000>; 494 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 495 clock-names = "dspi"; 496 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 497 QORIQ_CLK_PLL_DIV(2)>; 498 spi-num-chipselects = <5>; 499 big-endian; 500 status = "disabled"; 501 }; 502 503 i2c0: i2c@2180000 { 504 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 reg = <0x0 0x2180000 0x0 0x10000>; 508 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 510 QORIQ_CLK_PLL_DIV(2)>; 511 dmas = <&edma0 1 38>, 512 <&edma0 1 39>; 513 dma-names = "rx", "tx"; 514 status = "disabled"; 515 }; 516 517 i2c1: i2c@2190000 { 518 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 reg = <0x0 0x2190000 0x0 0x10000>; 522 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 524 QORIQ_CLK_PLL_DIV(2)>; 525 scl-gpios = <&gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 526 dmas = <&edma0 1 36>, 527 <&edma0 1 37>; 528 dma-names = "rx", "tx"; 529 status = "disabled"; 530 }; 531 532 i2c2: i2c@21a0000 { 533 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 reg = <0x0 0x21a0000 0x0 0x10000>; 537 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 539 QORIQ_CLK_PLL_DIV(2)>; 540 scl-gpios = <&gpio3 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 541 dmas = <&edma0 1 34>, 542 <&edma0 1 35>; 543 dma-names = "rx", "tx"; 544 status = "disabled"; 545 }; 546 547 i2c3: i2c@21b0000 { 548 compatible = "fsl,ls1046a-i2c", "fsl,vf610-i2c"; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 reg = <0x0 0x21b0000 0x0 0x10000>; 552 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 554 QORIQ_CLK_PLL_DIV(2)>; 555 scl-gpios = <&gpio3 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 556 dmas = <&edma0 1 40>, 557 <&edma0 1 41>; 558 dma-names = "rx", "tx"; 559 status = "disabled"; 560 }; 561 562 duart0: serial@21c0500 { 563 compatible = "fsl,ns16550", "ns16550a"; 564 reg = <0x00 0x21c0500 0x0 0x100>; 565 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 567 QORIQ_CLK_PLL_DIV(2)>; 568 status = "disabled"; 569 }; 570 571 duart1: serial@21c0600 { 572 compatible = "fsl,ns16550", "ns16550a"; 573 reg = <0x00 0x21c0600 0x0 0x100>; 574 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 576 QORIQ_CLK_PLL_DIV(2)>; 577 status = "disabled"; 578 }; 579 580 duart2: serial@21d0500 { 581 compatible = "fsl,ns16550", "ns16550a"; 582 reg = <0x0 0x21d0500 0x0 0x100>; 583 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 585 QORIQ_CLK_PLL_DIV(2)>; 586 status = "disabled"; 587 }; 588 589 duart3: serial@21d0600 { 590 compatible = "fsl,ns16550", "ns16550a"; 591 reg = <0x0 0x21d0600 0x0 0x100>; 592 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 594 QORIQ_CLK_PLL_DIV(2)>; 595 status = "disabled"; 596 }; 597 598 gpio0: gpio@2300000 { 599 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 600 reg = <0x0 0x2300000 0x0 0x10000>; 601 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 602 gpio-controller; 603 #gpio-cells = <2>; 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 }; 607 608 gpio1: gpio@2310000 { 609 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 610 reg = <0x0 0x2310000 0x0 0x10000>; 611 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 612 gpio-controller; 613 #gpio-cells = <2>; 614 interrupt-controller; 615 #interrupt-cells = <2>; 616 }; 617 618 gpio2: gpio@2320000 { 619 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 620 reg = <0x0 0x2320000 0x0 0x10000>; 621 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 622 gpio-controller; 623 #gpio-cells = <2>; 624 interrupt-controller; 625 #interrupt-cells = <2>; 626 }; 627 628 gpio3: gpio@2330000 { 629 compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 630 reg = <0x0 0x2330000 0x0 0x10000>; 631 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 632 gpio-controller; 633 #gpio-cells = <2>; 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 }; 637 638 lpuart0: serial@2950000 { 639 compatible = "fsl,ls1021a-lpuart"; 640 reg = <0x0 0x2950000 0x0 0x1000>; 641 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 643 QORIQ_CLK_PLL_DIV(1)>; 644 clock-names = "ipg"; 645 dmas = <&edma0 1 32>, 646 <&edma0 1 33>; 647 dma-names = "rx", "tx"; 648 status = "disabled"; 649 }; 650 651 lpuart1: serial@2960000 { 652 compatible = "fsl,ls1021a-lpuart"; 653 reg = <0x0 0x2960000 0x0 0x1000>; 654 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 656 QORIQ_CLK_PLL_DIV(2)>; 657 clock-names = "ipg"; 658 dmas = <&edma0 1 30>, 659 <&edma0 1 31>; 660 dma-names = "rx", "tx"; 661 status = "disabled"; 662 }; 663 664 lpuart2: serial@2970000 { 665 compatible = "fsl,ls1021a-lpuart"; 666 reg = <0x0 0x2970000 0x0 0x1000>; 667 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 669 QORIQ_CLK_PLL_DIV(2)>; 670 clock-names = "ipg"; 671 dmas = <&edma0 1 28>, 672 <&edma0 1 29>; 673 dma-names = "rx", "tx"; 674 status = "disabled"; 675 }; 676 677 lpuart3: serial@2980000 { 678 compatible = "fsl,ls1021a-lpuart"; 679 reg = <0x0 0x2980000 0x0 0x1000>; 680 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 682 QORIQ_CLK_PLL_DIV(2)>; 683 clock-names = "ipg"; 684 dmas = <&edma0 1 26>, 685 <&edma0 1 27>; 686 dma-names = "rx", "tx"; 687 status = "disabled"; 688 }; 689 690 lpuart4: serial@2990000 { 691 compatible = "fsl,ls1021a-lpuart"; 692 reg = <0x0 0x2990000 0x0 0x1000>; 693 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 695 QORIQ_CLK_PLL_DIV(2)>; 696 clock-names = "ipg"; 697 dmas = <&edma0 1 24>, 698 <&edma0 1 25>; 699 dma-names = "rx", "tx"; 700 status = "disabled"; 701 }; 702 703 lpuart5: serial@29a0000 { 704 compatible = "fsl,ls1021a-lpuart"; 705 reg = <0x0 0x29a0000 0x0 0x1000>; 706 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 708 QORIQ_CLK_PLL_DIV(2)>; 709 clock-names = "ipg"; 710 dmas = <&edma0 1 22>, 711 <&edma0 1 23>; 712 dma-names = "rx", "tx"; 713 status = "disabled"; 714 }; 715 716 wdog0: watchdog@2ad0000 { 717 compatible = "fsl,ls1046a-wdt", "fsl,imx21-wdt"; 718 reg = <0x0 0x2ad0000 0x0 0x10000>; 719 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 721 QORIQ_CLK_PLL_DIV(2)>; 722 big-endian; 723 }; 724 725 edma0: dma-controller@2c00000 { 726 #dma-cells = <2>; 727 compatible = "fsl,vf610-edma"; 728 reg = <0x0 0x2c00000 0x0 0x10000>, 729 <0x0 0x2c10000 0x0 0x10000>, 730 <0x0 0x2c20000 0x0 0x10000>; 731 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 733 interrupt-names = "edma-tx", "edma-err"; 734 dma-channels = <32>; 735 big-endian; 736 clock-names = "dmamux0", "dmamux1"; 737 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 738 QORIQ_CLK_PLL_DIV(2)>, 739 <&clockgen QORIQ_CLK_PLATFORM_PLL 740 QORIQ_CLK_PLL_DIV(2)>; 741 }; 742 743 aux_bus: bus { 744 #address-cells = <2>; 745 #size-cells = <2>; 746 compatible = "simple-bus"; 747 ranges; 748 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; 749 750 usb0: usb@2f00000 { 751 compatible = "snps,dwc3"; 752 reg = <0x0 0x2f00000 0x0 0x10000>; 753 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 754 dr_mode = "host"; 755 snps,quirk-frame-length-adjustment = <0x20>; 756 snps,dis_rxdet_inp3_quirk; 757 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 758 usb3-lpm-capable; 759 }; 760 761 usb1: usb@3000000 { 762 compatible = "snps,dwc3"; 763 reg = <0x0 0x3000000 0x0 0x10000>; 764 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 765 dr_mode = "host"; 766 snps,quirk-frame-length-adjustment = <0x20>; 767 snps,dis_rxdet_inp3_quirk; 768 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 769 usb3-lpm-capable; 770 }; 771 772 usb2: usb@3100000 { 773 compatible = "snps,dwc3"; 774 reg = <0x0 0x3100000 0x0 0x10000>; 775 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 776 dr_mode = "host"; 777 snps,quirk-frame-length-adjustment = <0x20>; 778 snps,dis_rxdet_inp3_quirk; 779 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 780 usb3-lpm-capable; 781 }; 782 783 sata: sata@3200000 { 784 compatible = "fsl,ls1046a-ahci"; 785 reg = <0x0 0x3200000 0x0 0x10000>, 786 <0x0 0x20140520 0x0 0x4>; 787 reg-names = "ahci", "sata-ecc"; 788 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 790 QORIQ_CLK_PLL_DIV(2)>; 791 }; 792 }; 793 794 msi1: msi-controller@1580000 { 795 compatible = "fsl,ls1046a-msi"; 796 msi-controller; 797 reg = <0x0 0x1580000 0x0 0x10000>; 798 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 802 }; 803 804 msi2: msi-controller@1590000 { 805 compatible = "fsl,ls1046a-msi"; 806 msi-controller; 807 reg = <0x0 0x1590000 0x0 0x10000>; 808 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 812 }; 813 814 msi3: msi-controller@15a0000 { 815 compatible = "fsl,ls1046a-msi"; 816 msi-controller; 817 reg = <0x0 0x15a0000 0x0 0x10000>; 818 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 822 }; 823 824 pcie1: pcie@3400000 { 825 compatible = "fsl,ls1046a-pcie"; 826 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 827 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 828 reg-names = "regs", "config"; 829 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 830 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 831 interrupt-names = "pme", "aer"; 832 #address-cells = <3>; 833 #size-cells = <2>; 834 device_type = "pci"; 835 num-viewport = <8>; 836 bus-range = <0x0 0xff>; 837 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 838 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 839 msi-parent = <&msi1>, <&msi2>, <&msi3>; 840 #interrupt-cells = <1>; 841 interrupt-map-mask = <0 0 0 7>; 842 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 843 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 844 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 845 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 846 big-endian; 847 status = "disabled"; 848 }; 849 850 pcie_ep1: pcie_ep@3400000 { 851 compatible = "fsl,ls1046a-pcie-ep"; 852 reg = <0x00 0x03400000 0x0 0x00100000>, 853 <0x40 0x00000000 0x8 0x00000000>; 854 reg-names = "regs", "addr_space"; 855 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 856 interrupt-names = "pme"; 857 num-ib-windows = <6>; 858 num-ob-windows = <8>; 859 big-endian; 860 status = "disabled"; 861 }; 862 863 pcie2: pcie@3500000 { 864 compatible = "fsl,ls1046a-pcie"; 865 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 866 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 867 reg-names = "regs", "config"; 868 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 869 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 870 interrupt-names = "pme", "aer"; 871 #address-cells = <3>; 872 #size-cells = <2>; 873 device_type = "pci"; 874 num-viewport = <8>; 875 bus-range = <0x0 0xff>; 876 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 877 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 878 msi-parent = <&msi2>, <&msi3>, <&msi1>; 879 #interrupt-cells = <1>; 880 interrupt-map-mask = <0 0 0 7>; 881 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 882 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 883 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 884 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 885 big-endian; 886 status = "disabled"; 887 }; 888 889 pcie_ep2: pcie_ep@3500000 { 890 compatible = "fsl,ls1046a-pcie-ep"; 891 reg = <0x00 0x03500000 0x0 0x00100000>, 892 <0x48 0x00000000 0x8 0x00000000>; 893 reg-names = "regs", "addr_space"; 894 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 895 interrupt-names = "pme"; 896 num-ib-windows = <6>; 897 num-ob-windows = <8>; 898 big-endian; 899 status = "disabled"; 900 }; 901 902 pcie3: pcie@3600000 { 903 compatible = "fsl,ls1046a-pcie"; 904 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 905 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 906 reg-names = "regs", "config"; 907 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 908 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 909 interrupt-names = "pme", "aer"; 910 #address-cells = <3>; 911 #size-cells = <2>; 912 device_type = "pci"; 913 num-viewport = <8>; 914 bus-range = <0x0 0xff>; 915 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ 916 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 917 msi-parent = <&msi3>, <&msi1>, <&msi2>; 918 #interrupt-cells = <1>; 919 interrupt-map-mask = <0 0 0 7>; 920 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 921 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 922 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 923 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 924 big-endian; 925 status = "disabled"; 926 }; 927 928 pcie_ep3: pcie_ep@3600000 { 929 compatible = "fsl,ls1046a-pcie-ep"; 930 reg = <0x00 0x03600000 0x0 0x00100000>, 931 <0x50 0x00000000 0x8 0x00000000>; 932 reg-names = "regs", "addr_space"; 933 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 934 interrupt-names = "pme"; 935 num-ib-windows = <6>; 936 num-ob-windows = <8>; 937 big-endian; 938 status = "disabled"; 939 }; 940 941 qdma: dma-controller@8380000 { 942 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; 943 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 944 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 945 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 946 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-names = "qdma-error", "qdma-queue0", 952 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 953 #dma-cells = <1>; 954 dma-channels = <8>; 955 block-number = <1>; 956 block-offset = <0x10000>; 957 fsl,dma-queues = <2>; 958 status-sizes = <64>; 959 queue-sizes = <64 64>; 960 big-endian; 961 }; 962 963 rcpm: wakeup-controller@1ee2140 { 964 compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+"; 965 reg = <0x0 0x1ee2140 0x0 0x4>; 966 #fsl,rcpm-wakeup-cells = <1>; 967 }; 968 969 ftm_alarm0: rtc@29d0000 { 970 compatible = "fsl,ls1046a-ftm-alarm"; 971 reg = <0x0 0x29d0000 0x0 0x10000>; 972 fsl,rcpm-wakeup = <&rcpm 0x20000>; 973 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 974 big-endian; 975 }; 976 }; 977 978 reserved-memory { 979 #address-cells = <2>; 980 #size-cells = <2>; 981 ranges; 982 983 bman_fbpr: bman-fbpr { 984 compatible = "shared-dma-pool"; 985 size = <0 0x1000000>; 986 alignment = <0 0x1000000>; 987 no-map; 988 }; 989 990 qman_fqd: qman-fqd { 991 compatible = "shared-dma-pool"; 992 size = <0 0x800000>; 993 alignment = <0 0x800000>; 994 no-map; 995 }; 996 997 qman_pfdr: qman-pfdr { 998 compatible = "shared-dma-pool"; 999 size = <0 0x2000000>; 1000 alignment = <0 0x2000000>; 1001 no-map; 1002 }; 1003 }; 1004 1005 firmware { 1006 optee { 1007 compatible = "linaro,optee-tz"; 1008 method = "smc"; 1009 }; 1010 }; 1011}; 1012 1013#include "qoriq-qman-portals.dtsi" 1014#include "qoriq-bman-portals.dtsi" 1015